TC74HCT652AP
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74HCT652AP
Octal Bus Transceiver/Register (3-state)
The TC74HCT652A is high speed CMOS OCTAL BUS
TRANSCEIVER/REGISTER fabricated with silicon gate C
2
MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
Its inputs are compatible with TTL, NMOS, and CMOS output
voltage levels.
This device is bus transceiver with 3-state outputs, D-type
flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the internal registers.
ALL inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Weight: 1.50 g (typ.)
Features (Note 1) (Note 2)
•
•
•
•
•
•
•
High speed: f
max
= 60 MHz (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 4
μA
(max) at Ta = 25°C
Compatible with TTL output: V
IH
= 2.0 V (min)
V
IL
= 0.8 V (max)
Output drive capability: 15 LSTTL loads
Symmetrical output impedance: |I
OH
| = I
OL
= 6 mA (min)
∼
Balanced propagation delays: t
pLH
−
t
pHL
Pin and function compatible with 74LS652
Note 1: Do not apply a signal to any bus terminal when it is in the out put mode. Damage may result.
Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or pull
down resistors.
Pin Assignment
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TC74HCT652AP
IEC Logic Symbol
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TC74HCT652AP
Truth Table
GAB
GBA
CAB
X
CBA
X
(Note)
SAB
X
SBA
X
A
Inputs
Z
X
Inputs
B
Inputs
Z
X
Outputs
L
H
L
H
Qn
L
H
Inputs
L
H
L
H
X
L
H
Outputs
Qn
Function
The output functions of A and B busses are
disabled.
Both A and B busses are used as inputs to the
internal flip-flops. Data on the bus will be stored
on the rising edge of the clock.
L
H
(Note)
X
X
X
(Note)
X
(Note)
X
L
X
L
H
The data on the A bus are displayed on the B bus.
H
H
X
(Note)
(Note)
X
(Note)
X
(Note)
X
(Note)
X
X
(Note)
L
X
L
H
X
L
H
Outputs
The data on the A bus are displayed on the B bus,
and are stored into the A storage flip-flops on the
rising edge of CAB.
The data in the A storage flip-flops are displayed
on the B bus.
The data on the A bus are stored into the A
storage flip-flops on the rising edge of CAB, and
the stored data propagate directly onto the B bus.
H
X
H
X
X
L
L
H
The data on the B bus are displayed on the A bus.
L
L
(Note)
X
(Note)
X
(Note)
X
(Note)
X
L
L
H
Qn
L
H
Outputs
Qn
The data on the B bus are displayed on the A bus,
and are stored into the B storage flip-flops on the
rising edge of CBA.
The data in the B storage flip-flops are displayed
on the A bus.
The data on the B bus are stored into the B
storage flip-flops on the rising edge of CBA, and
the stored data propagate directly onto the A bus.
The data stored to the internal flip-flops are
displayed at the A and B bus respectively.
X
H
X
X
(Note)
H
H
L
X
(Note)
H
H
X: Don’t care
Qn: The data stored into the internal flip-flops by most recent low to high transition of the clock inputs.
Z: High impedance
Note:
The clock are not internally gated with either GAB or
GBA
. Therefore, data on the A and/or B busses may
be clocked into the storage flip-flops at any time.
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TC74HCT652AP
Timing Chart
System Diagram
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TC74HCT652AP
Absolute Maximum Ratings (Note 1)
Characteristics
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Rating
−
0.5~7.0
−
0.5~V
CC
+
0.5
−
0.5~V
CC
+
0.5
±
20
±
20
±
35
±
75
Unit
V
V
V
mA
mA
mA
mA
(Note 2)
mW
°C
500 (DIP)
−
65
∼
150
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta
= −40
to 65°C. From Ta
=
65 to 85°C a derating factor of
−10
mW/°C should be
applied up to 300 mW.
Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise and fall time
Symbol
V
CC
V
IN
V
OUT
T
opr
t
r
, t
f
Rating
4.5~5.5
0~V
CC
0~V
CC
−
40~85
Unit
V
V
V
°C
ns
0~500
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
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DIY/Open Source Hardware
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