TMP86P808NG datasheet, PDF - EEWORLD Datasheet

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TMP86P808NG: Description8 Bit Microcontroller; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，160 Pages; ManufacturerToshiba Semiconductor; Websitehttp://toshiba-semicon-storage.com/; Environmental Compliance

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TMP86P808NG Overview

8 Bit Microcontroller

TMP86P808NG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	DIP
package instruction	SDIP, SDIP30,.4
Contacts	30
Reach Compliance Code	unknow
Has ADC	YES
Other features	ALSO OPERATES AT 2.7V MINIMUM SUPPLY AT 8 MHZ
Address bus width
bit size	8
CPU series	TLCS-870/C
maximum clock frequency	16 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	R-PDIP-T30
JESD-609 code	e2/e6
length	27.4 mm
Number of I/O lines	24
Number of terminals	30
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	SDIP
Encapsulate equivalent code	SDIP30,.4
Package shape	RECTANGULAR
Package form	IN-LINE, SHRINK PITCH
power supply	3/5 V
Certification status	Not Qualified
RAM (bytes)	256
rom(word)	8192
ROM programmability	OTPROM
Maximum seat height	4.45 mm
speed	16 MHz
Maximum slew rate	9 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER/TIN BISMUTH
Terminal form	THROUGH-HOLE
Terminal pitch	1.778 mm
Terminal location	DUAL
width	15.24 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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8 Bit Microcontroller

TLCS-870/C Series

TMP86P808NG

TMP86P808NG

The information contained herein is subject to change without notice. 021023 _ D

TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless,

semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and

vulnerability to physical stress.

It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards

of safety in making a safe design for the entire system, and to avoid situations in which a malfunction

or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to

property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating

ranges as set forth in the most recent TOSHIBA products specifications.

Also, please keep in mind the precautions and conditions set forth in the

“Handling

Guide for

Semiconductor Devices,” or

“TOSHIBA

Semiconductor Reliability Handbook” etc. 021023_A

The Toshiba products listed in this document are intended for usage in general electronics applications

(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic

appliances, etc.).

These Toshiba products are neither intended nor warranted for usage in equipment that requires

extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of

human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,

combustion control instruments, medical instruments, all types of safety devices, etc. Unintended

Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B

The products described in this document shall not be used or embedded to any downstream products

of which manufacture, use and/or sale are prohibited under any applicable laws and regulations.

060106_Q

The information contained herein is presented only as a guide for the applications of our products. No

responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third

parties which may result from its use. No license is granted by implication or otherwise under any

patent or patent rights of TOSHIBA or others. 021023_C

The products described in this document may include products subject to the foreign exchange and

foreign trade laws. 021023_F

For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3

of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S

Table of Contents

TMP86P808NG

1.1

1.2

1.3

1.4

Features

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Assignment

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Block Diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Names and Functions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operational Description

2.1

CPU Core Functions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Memory Address Map...............................................................................................................................

Program Memory (OTP)

........................................................................................................................... 7

Data Memory (RAM)

................................................................................................................................. 7

Clock Generator........................................................................................................................................

Timing Generator

.................................................................................................................................... 10

Operation Mode Control Circuit

.............................................................................................................. 11

Single-clock mode

Dual-clock mode

STOP mode

Configuration of timing generator

Machine cycle

2.2

2.1.1

2.1.2

2.1.3

2.2.1

2.2.2

2.2.3

System Clock Controller

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.2.1

2.2.2.2

2.2.3.1

2.2.3.2

2.2.3.3

2.2.4.1

2.2.4.2

2.2.4.3

2.2.4.4

2.2.4

Operating Mode Control

......................................................................................................................... 16

STOP mode

IDLE1/2 mode and SLEEP1/2 mode

IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)

SLOW mode

2.3

Reset Circuit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

External Reset Input

...............................................................................................................................

Address trap reset

..................................................................................................................................

Watchdog timer reset..............................................................................................................................

System clock reset..................................................................................................................................

2.3.1

2.3.2

2.3.3

2.3.4

Interrupt Control Circuit

3.1

3.2

3.3

3.4

Interrupt latches (IL15 to IL2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Interrupt enable register (EIR)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Interrupt Source Selector (INTSEL).

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Interrupt Sequence

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Interrupt acceptance processing is packaged as follows........................................................................

Saving/restoring general-purpose registers

............................................................................................ 38

Interrupt return

........................................................................................................................................ 40

Using PUSH and POP instructions

Using data transfer instructions

3.2.1

3.2.2

Interrupt master enable flag (IMF)

.......................................................................................................... 34

Individual interrupt enable flags (EF15 to EF4)

...................................................................................... 34

3.4.1

3.4.2

3.4.3

3.5.1

3.5.2

3.4.2.1

3.4.2.2

3.5

Software Interrupt (INTSW)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Address error detection

.......................................................................................................................... 40

Debugging

.............................................................................................................................................. 41

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