SN7472N3 datasheet, PDF - EEWORLD Datasheet

SN7472N3: DescriptionAND-Gated J-K Master-Slave Flip-Flop with Preset and Clear 14-PDIP 0 to 70; Categorylogic; File Size574KB，12 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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SN7472N3 Overview

AND-Gated J-K Master-Slave Flip-Flop with Preset and Clear 14-PDIP 0 to 70

Parameter Name	Attribute value
Brand Name	Texas Instruments
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Texas Instruments
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14
Reach Compliance Code	not_compliant
Other features	WITH MASTER SLAVE OPERATION; 3 J & 3 K INPUTS ANDED
series	7472
JESD-30 code	R-PDIP-T14
length	19.305 mm
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	1
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
propagation delay (tpd)	40 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	NEGATIVE EDGE
width	7.62 mm
minfmax	15 MHz
Base Number Matches	1

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