September 2006
H Y S6 4D 32 000H D L– [ 5 / 6 ] – C
H Y S6 4D 64 020H D L– [ 5 / 6 ] – C
200-Pin Small-Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.11
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
HYS64D32000HDL–[5/6]–C, HYS64D64020HDL–[5/6]–C
Revision History: 2006-09, Rev. 1.11
Page
All
22
Subjects (major changes since last revision)
Adapted internet edition
updated
t
RFC
for DDR400 from 70 ns to 65 ns
Previous Revision: Rev. 1.10, 2005-12
Previous Revision: Rev. 1.0, 2005-04
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03292006-428D-USV0
2
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
1
Overview
This chapter gives an overview of the 200-Pin Small-Outline Dual-In-Line Memory Modules product family and describes its
main characteristics.
1.1
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Features
Non-parity 200-Pin Small-Outline Dual-In-Line Memory Modules
One rank 32M
×64
and two ranks 64M
×64
organization
Standard Double Data Rate Synchronous DRAMs ( )
Single +2.5 V (± 0.2 V) power supply and +2.6 V (± 0.1 V) for DDR400
Built with 512 Mbit s organized as
×16
in P–TSOPII–66 packages
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E
2
PROM
Standard form factor: 67.60 mm
×
31.75 mm
×
3.80 mm
Standard reference layout Raw Cards A and C
Gold plated contacts
RoHS Compliant Products
1)
TABLE 1
Performance
Part Number Speed Code
Speed Grade
max. Clock
Frequency
Component
Module
@CL3
@CL2.5
@CL2
f
CK3
f
CK2.5
f
CK2
–5
DDR400B
PC3200–3033
200
166
133
–6
DDR333B
PC2700–2533
166
166
133
–7
DDR266A
PC2100–2033
–
143
133
Unit
—
—
MHz
MHz
MHz
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.11, 2006-09
03292006-428D-USV0
3
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
1.2
Description
capacitors are mounted on the PC board. The DIMMs feature
serial presence detect based on a serial E
2
PROM device
using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and the second
128 bytes are available to the customer.
The HYS64D32000HDL–[5/6]–C and HYS64D64020HDL–
[5/6]–C are industry standard 200-Pin Small-Outline
Dual-In-Line Memory Modules (SO-DIMMs) organized as
64M
×64.
The memory array is designed with Double Data
Rate Synchronous DRAMs ( ). A variety of de coupling
TABLE 2
Ordering Information for Lead-Free (RoHS Compliant Products)
Product Type
1)
PC3200 (CL=3.0)
HYS64D32000HDL–5–C
HYS64D64020HDL–5–C
PC2700 (CL=2.5)
HYS64D32000HDL–6–C
HYS64D64020HDL–6–C
PC2700S–2533–1–C0
PC2700S-2533–1–A0
One rank 256MB SO-DIMM
Two ranks 512MB SO-DIMM
512 MBit (×16)
512 MBit (×16)
PC3200S-3033–1–C0
PC3200S-3033–1–A0
One rank 256MB SO-DIMM
Two ranks 512MB SO-DIMM
512 MBit (×16)
512 MBit (×16)
Compliance Code
2)
Description
SDRAM Technology
1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example:
HYS64D64020GDL–5–B, indicating Rev.B die are used for SDRAM components.
2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC3200”), the latencies (for example
“30330” means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Pre-charge latency of 3 clocks), JEDEC
SPD code definition version 1, and the Raw Card used for this module.
Rev. 1.11, 2006-09
03292006-428D-USV0
4
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
2
Pin Configuration
explained in
Table 4
and
Table 5
respectively. The pin
numbering is depicted in
Figure 1.
The pin configuration of the Unbuffered Small Outline DDR
SDRAM DIMM is listed by function in
Table 3
(200 pins). The
abbreviations used in columns Pin and Buffer Type are
TABLE 3
Pin Configuration of SO-DIMM
Pin#
Clock Signals
35
160
89
37
158
91
96
95
CK0
CK1
CK2
NC
CK0
CK1
CK2
NC
CKE0
CKE1
NC
Control Signals
121
122
S0
S1
NC
118
120
119
117
116
RAS
CAS
WE
BA0
BA1
I
I
NC
I
I
I
I
I
SSTL
SSTL
–
SSTL
SSTL
SSTL
SSTL
SSTL
Chip Select Rank 0
Chip Select Rank 1
Note: 2-ranks module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
Bank Address Bus 1:0
I
I
I
NC
I
I
I
NC
I
I
NC
SSTL
SSTL
SSTL
–
SSTL
SSTL
SSTL
–
SSTL
SSTL
–
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-ranks module
Note: 1-rank module
Complement Clock
Complement Clock
Complement Clock
Clock Signal
Clock Signal
Clock Signal
Name
Pin
Type
Buffer
Type
Function
Address Signals
Rev. 1.11, 2006-09
03292006-428D-USV0
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