FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-13104-3E
Memory FRAM
CMOS
1 M Bit (64 K
×
16)
MB85R1002
■
DESCRIPTIONS
The MB85R1002 is an FRAM (Ferroelectric Random Access Memory) chip consisting of 65,536 words x 16 bits
of non-volatile memory cells created using ferroelectric process and silicon gate CMOS process technologies.
The MB85R1002 is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85R1002 can be used for at least 10
10
read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E
2
PROM.
The MB85R1002 uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM.
■
FEATURES
•
•
•
•
•
•
•
Bit configuration
Read/write endurance
Operating power supply voltage
Operating temperature range
Data retention
LB and UB data byte control
Package
: 65,536 words
×
16 bits
: 10
10
times/bit (Min)
: 3.0 V to 3.6 V
:
−
20 °C to +85 °C
: 10 years (+55
°C)
: 48-pin plastic TSOP (1)
: 48-pin plastic FBGA
Copyright©2005-2007 FUJITSU LIMITED All rights reserved
MB85R1002
■
FUNCTION TRUTH TABLE
Mode
CE1
CE2
WE
OE
LB
UB
I/O1 to I/O8 I/O9 to I/O16
Supply Current
H
Standby Pre-charge
X
X
X
Read
X
L
X
X
H
X
X
H
X
H
X
X
H
X
L
X
X
X
H
L
L
H
L
X
X
X
H
L
H
L
L
H
L
L
H
L
L
H
L
Dout
Dout
High-Z
Dout
Dout
High-Z
Din
Din
High-Z
Din
Din
High-Z
Dout
High-Z
Dout
Dout
High-Z
Dout
Din
High-Z
Din
Din
High-Z
Din
Operation
(I
CC
)
High-Z
High-Z
Standby
(I
SB
)
L
Read
(Pseudo-SRAM,
OE control*
1
)
L
H
H
L
H
L
Write
H
L
L
X
L
H
L
Write
(Pseudo-SRAM,
WE control*
2
)
L
H
H
L
H
Notes : L = V
IL
, H = V
IH
, X can be either V
IL
or V
IH
, High-Z = High Impedance
: Latch address and latch data at falling edge,
: Latch address and latch data at rising edge
*1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read.
*2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write.
5
Microcontroller MCU
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