PRELIMINARY
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER
W/INTERNAL TERMINATION
ICS889872
Features
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Three LVDS outputs
Frequency divide select options: ÷4, ÷6: >2GHz,
÷8, ÷16: >1.6GHz
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
Output frequency: >2GHz
Cycle-to-cycle jitter: 1ps (typical)
Total jitter: 10ps (typical)
Output skew: 7ps (typical), QA/nQA outputs
Part-to-part skew: 250ps (typical)
Propagation Delay: 750ps (typical), QA/nQA outputs
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
General Description
The ICS889872 is a high speed Differential-to-
LVDS Buffer/Divider w/Internal Termination and is a
HiPerClockS™
member of the HiPerClockS™family of high
performance clock solutions from IDT. The
ICS889872 has a selectable ÷2, ÷4, ÷8, ÷16 output
dividers. The clock input has internal termination resistors,
allowing it to interface with several differential signal types while
minimizing the number of required external components. The
device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
ICS
Block Diagram
Pin Assignment
GND
nRESET/
nDISABLE
Enable
FF
QB0 1
nQB0
Enable
MUX
2
16 15 14 13
12 IN
11 V
T
10 V
REF_AC
9 nIN
5
QA
QB1 3
QA
nQA
nQB1 4
6
nQA
V
DD
S0
S1
7
V
DD
8
nRESET/
nDISABLE
IN
50Ω
QB0
÷2, ÷4,
÷8, ÷16
nQB0
V
T
50Ω
nIN
V
REF_AC
S1
Decoder
S0
ICS889872
QB1
nQB1
16-Lead VFQFN
3mm x 3mm x 0.95mm package body
K Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™
LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
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ICS889872
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Table 1. Pin Descriptions
Number
1, 2
Name
QB0, nQB0
Output
Type
Description
Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be
terminated with 100W across the pin (QB0/nQB0).
LVDS interface levels.
Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be
terminated with 100W across the pin (QB1nQB1).
LVDS interface levels.
Differential undivided output pair. LVDS interface levels.
Power supply pins.
Output reset and enable/disable pin. When LOW, resets the divider select,
and align Bank A and Bank B edges. In addition, when LOW, Bank A and
Bank B will be disabled. Input threshold is V
DD
/2V.
Includes a 37k
Ω
pullup resistor. LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. RT = 50
Ω
termination to V
T
.
Reference voltage for AC-coupled applications. Equal to V
DD
– 1.4V
(approx.). Maximum sink/source current is 0.5mA.
Termination input. Leave pin floating.
Non-inverting LVPECL differential clock input.
RT = 50
Ω
termination to V
T
.
Power supply ground.
Pullup
Select pins. Logic HIGH if left unconnected (÷16 mode). S0 = LSB.
Input threshold is VDD/2. 37kW pullup resistor.
LVCMOS/LVTTL interface levels.
3, 4
5, 6
7, 14
QB1, nQB1
QA, nQA
V
DD
nRESET/
nDISABLE
nIN
V
REF_AC
V
T
IN
GND
S1, S0
Output
Output
Power
8
Input
Pullup
9
10
11
12
13
15, 16
Input
Output
Input
Input
Power
Input
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
Ω
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DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Function Tables
Table 3A. Control Input Function Table
Input
nRESET
0
1
QA, QBx
Disabled; LOW
Enabled
Outputs
nQA, nQBx
Disabled; HIGH
Enabled
NOTE: After nRESET switches, the clock outputs are disabled or
enabled following a falling input clock edge as shown in
Figure 1.
Figure 1. nRESET Timing Diagram
V
DD
/2
t
RR
nRESET
IN
nIN
V
IN
Swing
t
PD
nQBx
QBx
QA
nQA
V
OUT
Swing
Table 3B. Truth Table
Inputs
nRESET/nDISABLE
1
1
1
1
0
S1
0
0
1
1
X
S0
0
1
0
1
X
Bank A
Input Clock
Input Clock
Input Clock
Input Clock
QA = LOW, nQA = HIGH; NOTE 1
Outputs
Bank B
Input Clock ÷2
Input Clock ÷4
Input Clock ÷8
Input Clock ÷16
QBx = LOW, nQBx = HIGH; NOTE 2
NOTE 1: On the next negative transition of the input signal.
NOTE 2: Asynchronous reset/disable function.Absolute Maximum Ratings
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DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
Operating Temperature Range, T
A
Package Thermal Impedance,
θ
JA
, (Junction-to-Ambient)
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±50mA
±100mA
± 0.5mA
-40°C to +85°C
51.5°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
80
Maximum
2.625
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
2
0
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
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DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Table 4C. Differential DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
I
IN
V
REF_AC
Parameter
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
Differential Input Voltage Swing
Input Current
Bias Voltage
(IN, nIN)
V
DD
– 1.35
(IN, nIN)
(IN, nIN)
(IN, nIN)
1.2
0
0.15
0.3
45
Test Conditions
Minimum
Typical
100
V
DD
V
DD
– 0.15
2.8
Maximum
Units
Ω
V
V
V
V
mA
V
Table 4D. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OUT
V
OH
V
OL
V
CCM
∆V
OCM
Parameter
Output Voltage Swing
Output High Voltage
Output Low Voltage
Output Common Mode Voltage
Change in Common Mode Voltage
0.925
1.35
50
Test Conditions
Minimum
Typical
350
1.475
Maximum
Units
mV
V
V
V
mV
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Parameter
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit(cc)
tjit(j)
t
RR
t
R
/ t
F
Symbol
Output Frequency
Input Frequency
Propagation Delay;
NOTE 1, 2
Output Skew;
NOTE 2, 3, 4
IN-to-Q
QB0-to-QB1
QA-to-QB
Test Conditions
÷2, ÷4
÷8, ÷16
Input Swing: <400mV
Input Swing:
≥400mV
Minimum
Typical
>2
>1.6
750
750
7
60
250
1
10
600
150
Maximum
Units
GHz
GHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
Part-to-Part Skew; NOTE 2, 4, 5
Cycle-to-Cycle Jitter; NOTE 2, 6
Total Jitter; NOTE 2
Reset Recovery Time; NOTE 2
Output Rise/Fall Time; NOTE 2
All parameters characterized at
≤
1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Specs are design targets.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 6: The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
IDT™ / ICS™
LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
5
ICS889872AK REV. A AUGUST 22, 2007
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