M463S3254CK1
Revision History
Revision 0.0 (July 2001)
• First published.
PC100/PC133
µSODIMM
Revision 0.1 (Aug. 2001)
• SPD correction
Revision 0.2 (Sept. 2001)
•
•
Redefined IDD1 & IDD4 in DC Characteristics
Changed the Notes in Operating AC Parameter.
< Before >
5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
< After >
5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.2 Sept. 2001
M463S3254CK1
M463S3254CK1 SDRAM
µ
SODIMM
GENERAL DESCRIPTION
The Samsung M463S3254CK1 is a 32M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M463S3254CK1 consists of four CMOS 32M x 16 bit with 4banks
Synchronous DRAMs in TSOP-II 400mil package and a 2K
EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy sub-
strate. Three 0.1uF bypass capacitors are mounted on the printed
circuit board in parallel for each SDRAM. The M463S3254CK1 is a
Small Outline Dual In-line Memory Module and is intended for
mounting into 144-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows the
same device to be useful for a variety of high bandwidth, high per-
formance memory system applications.
PC100/PC133
µSODIMM
32Mx64 SDRAM
µSODIMM
based on 32Mx16, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
FEATURE
• Performance range
Part No.
M464S3254CK1-C7C /L7C
M464S3254CK1-C7A /L7A
M464S3254CK1-C1H /L1H
M464S3254CK1-C1L /L1L
•
•
•
•
•
Max Freq. (Speed)
133MHz (7.5ns @ CL2)
133MHz (7.5ns @ CL3)
100MHz (10ns @ CL2)
100MHz (10ns @ CL3)
Burst mode operation
Auto & self refresh capability (8192 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB :
Height (30mm)
, double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front Pin
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
V
SS
DQM0
DQM1
V
DD
A0
A1
A2
V
SS
DQ8
DQ9
DQ10
DQ11
V
DD
DQ12
DQ13
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
V
SS
DQM4
DQM5
V
DD
A3
A4
A5
V
SS
DQ40
DQ41
DQ42
DQ43
V
DD
DQ44
DQ45
Pin Front
51
53
55
57
59
DQ14
DQ15
V
SS
NC
NC
Pin
52
54
56
58
60
Back
Pin
Front
DQ21
DQ22
DQ23
V
DD
A6
A8
V
SS
A9
A10/AP
V
DD
DQM2
DQM3
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
**SDA
V
DD
Pin
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Back
DQ53
DQ54
DQ55
V
DD
A7
BA0
V
SS
BA1
A11
V
DD
DQM6
DQM7
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
**SCL
V
DD
DQ46 95
DQ47 97
V
SS
99
NC 101
NC 103
105
107
Voltage Key
109
CLK0 62 CKE0 111
V
DD
V
DD
113
64
RAS 66 CAS 115
68 *CKE1 117
WE
70
CS0
A12 119
*CS1 72 *A13 121
74 *CLK1 123
DU
76
V
SS
V
SS
125
78
NC
NC 127
80
NC
NC 129
82
V
DD
V
DD
131
DQ16 84 DQ48 133
DQ17 86 DQ49 135
DQ18 88 DQ50 137
DQ19 90 DQ51 139
92
V
SS
141
V
SS
DQ20 94 DQ52 143
PIN NAMES
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
CLK0
CKE0
CS0
RAS
CAS
WE
DQM0 ~ 7
V
DD
V
SS
SDA
SCL
DU
NC
Function
Address input (Multiplexed)
Select bank
Data input/output
Clock input
Clock enable input
Chip select input
Row address storbe
Column address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Serial data I/O
Serial clock
Don′t use
No connection
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
* These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.2 Sept. 2001
M463S3254CK1
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
PC100/PC133
µSODIMM
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+t
SS
prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A12
BA0 ~ BA1
RAS
CAS
WE
DQM0 ~ 7
DQ
0
~
63
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
V
DD
/V
SS
Rev. 0.2 Sept. 2001