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SY10E151

Description
6-BIT D REGISTER
File Size90KB,4 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet View All

SY10E151 Overview

6-BIT D REGISTER

NOT RECOMMENDED FOR NEW DESIGNS
Micrel, Inc.
6-BIT D
REGISTER
SY10E151
SY100E151
SY10E151
SY100E151
FEATURES
s
1100MHz toggle frequency
s
Extended 100E V
EE
range of –4.2V to –5.46V
s
s
s
s
Differential outputs
Asynchronous Master Reset
Dual clocks
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E151
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E151 offer 6 edge-triggered, high-speed,
master-slave D-type flip-flops with differential outputs,
designed for use in new, high-performance ECL systems.
The two external clock signals (CLK
1
, CLK
2
) are gated
through a logical OR operation before use as clocking
control for the flip-flops. Data is clocked into the flip-flops
on the rising edge of either CLK
1
or CLK
2
(or both). When
both CLK
1
and CLK
2
are at a logic LOW, data enters the
master and is transferred to the slave when either CLK
1
or
CLK
2
(or both) go HIGH.
The MR (Master Reset) signal operates asynchronously
to make all Q outputs go to a logic LOW.
BLOCK DIAGRAM
D
0
Q
0
R
D
1
D
R
D
2
D
R
D
3
D
R
D
4
D
R
D
5
D
R
CLK
1
CLK
2
M
R
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
PIN NAMES
Pin
D
Function
Data Inputs
Clock Inputs
Master Reset
True Outputs
Inverting Outputs
V
CC
to Output
D
0
–D
5
CLK
1
, CLK
2
MR
Q
0
–Q
5
Q
0
–Q
5
V
CCO
M9999-052108
hbwhelp@micrel.com or (408) 955-1690
Rev.: H
Amendment: /0
1
Issue Date: May 2008
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