IS62LV5128LL
512K x 8 LOW POWER and LOW Vcc
CMOS STATIC RAM
FEATURES
• Access times of 70, 85 ns
•
CMOS low power operation:
— 135 mW (typical) operating
— 16.5 µW (typical) standby
• Low data retention voltage: 2V (min.)
• Output Enable (OE) and Chip Enable
(CE) inputs for ease in applications
• TTL compatible inputs and outputs
• Fully static operation:
— No clock or refresh required
• Single 2.7V (min) to 3.15V (max) V
CC
power supply
• Available in 36-pin mini BGA
ISSI
DESCRIPTION
®
MAY 2001
The
ISSI
IS62LV5128LL is a low voltage, 524,288 words by
8 bits, CMOS SRAM. It is fabricated using
ISSI
’
s low voltage,
six transistor (6T), CMOS technology. The device is targeted to
satisfy the demands of the state-of-the-art technologies
such as cell phones and pagers.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels. Additionally, easy memory
expansion is provided by using Chip Enable and Output
Enable inputs,
CE
and
OE.
The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS62LV5128LL is available in a 36-pin mini BGA
package (8mm x 10mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K x 8
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
ISSI
reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
05/04/01
1
IS62LV5128LL
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
V
CC
T
BIAS
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
Vcc related to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
Value
–0.5 to Vcc + 0.3
–0.3 to +3.3
–40 to +85
–65 to +150
1
Unit
V
V
°C
°C
W
ISSI
®
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 3.0V.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Test Conditions
V
CC
= 3.0V, I
OH
= –1.0 mA
V
CC
= 3.0V, I
OL
= 2.1 mA
Min.
2.2
—
2.2
–0.2
–1
–1
Max.
—
0.4
V
CC
+ 0.3
0.4
1
1
Unit
V
V
V
V
µA
µA
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, O
UTPUTS
Disabled
Note:
1. V
IL
= –2.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
05/04/01
3
IS62LV5128LL
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-70
Symbol Parameter
I
CC
Vcc Dynamic
Operating
Supply Current
Operating Supply
Current
TTL Standby
Current
(TTL Inputs)
CMOS Standby
Current
(CMOS Inputs)
Test Conditions
V
CC
= Max., CE = V
IL
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max.,
I
OUT
= 0 mA, f = 0
V
CC
= Max.,
V
IN
= V
IH
or V
IL
,
CE1
≥
V
IH
, f = 0
V
CC
= Max., f = 0
CE1
≥
V
CC
– 0.2V,
or V
IN
≥
V
CC
– 0.2V,
V
IN
≤
0.2V
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
Min.
—
—
—
—
—
—
—
—
Max.
40
45
5
5
0.4
1.0
10
10
Min.
—
—
—
—
—
—
—
—
-85
ISSI
Max.
35
40
5
5
0.4
1.0
10
10
®
Unit
mA
I
CC
1
I
SB
1
mA
mA
I
SB
2
µA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-70
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
OE
to High-Z Output
OE
to Low-Z Output
CE
to Low-Z Output
CE
to High-Z Output
Min.
70
—
10
—
—
—
5
10
0
Max.
—
70
—
70
35
25
—
—
25
Min.
85
—
15
—
—
—
5
10
0
-85
Max.
—
85
—
85
40
25
—
—
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
HZOE
(2)
t
LZOE
(2)
t
LZCE
(2)
t
HZCE
(2)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
05/04/01
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