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SPC582B60E1L0X1Y

Description
RISC MICROCONTROLLER
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size2MB,102 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Download Datasheet Parametric View All

SPC582B60E1L0X1Y Overview

RISC MICROCONTROLLER

SPC582B60E1L0X1Y Parametric

Parameter NameAttribute value
MakerSTMicroelectronics
package instructionHTFQFP,
Reach Compliance Codecompliant
Has ADCYES
Address bus width
bit size32
maximum clock frequency40 MHz
DMA channelYES
External data bus width
length10 mm
Number of terminals64
PWM channelYES
encapsulated codeHTFQFP
Package shapeSQUARE
Package formFLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
speed64 MHz
Maximum supply voltage1.26 V
Minimum supply voltage1.14 V
Nominal supply voltage1.2 V
surface mountYES
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
width10 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER RISC
Base Number Matches1
SPC582B60x, SPC582B54x,
SPC582B50x
32-bit Power Architecture
®
microcontroller for automotive ASIL-B
applications
Datasheet
-
production data
– Cyclic redundancy check (CRC) unit
– End-to-end Error Correction Code
(e2eECC) logic
Crossbar switch architecture for concurrent
access to peripherals, Flash, or RAM from
multiple bus masters with end-to-end ECC
Body cross triggering unit (BCTU)
– Triggers ADC conversions from any eMIOS
channel
– Triggers ADC conversions from up to 2
dedicated PIT_RTIs
– 1 event configuration register dedicated to
each timer event allows to define the
corresponding ADC channel
– Synchronization with ADC to avoid collision
1 enhanced 12-bit SAR analog-to-digital
converters
– Up to 27 channels
– enhanced diagnosis feature
Communication interfaces
– 6 LINFlexD modules
– 4 deserial serial peripheral interface (DSPI)
modules
– 7 MCAN interfaces with advanced shared
memory scheme and ISO CAN FD support
Dual phase-locked loops with stable clock
domain for peripherals and FM modulation
domain for computational shell
Nexus Class 3 debug and trace interface
Boot assist Flash (BAF) supports factory
programming using a serial bootload through
the asynchronous CAN or LIN/UART.
Enhanced modular IO subsystem (eMIOS): up
to 32 timed I/O channels with 16-bit counter
resolution
Advanced and flexible supply scheme
– On-chip voltage regulator for 1.2 V core
logic supply.
Junction temperature range -40 °C to 150 °C
eTQFP64 (10 x 10 x 1.0 mm)
eTQFP100 (14 x 14 x 1.0 mm)
Features
AEC-Q100 qualified
High performance e200z2 single core
– 32-bit Power Architecture technology CPU
– Core frequency as high as 80 MHz
– Variable Length Encoding (VLE)
– Floating Point, End-to-End Error Correction
1088 KB (1024 KB code flash + 64 KB data
flash) on-chip flash memory: supports read
during program and erase operations, and
multiple blocks allowing EEPROM emulation
96 KB on-chip general-purpose SRAM
Multi-channel direct memory access controller
(eDMA) with 16 channels
1 interrupt controller (INTC)
Comprehensive new generation ASIL-B safety
concept
– ASIL-B of ISO 26262
– FCCU for collection and reaction to failure
notifications
– Memory Error Management Unit (MEMU)
for collection and reporting of error events
in memories
June 2018
This is information on a product in full production.
DS11597 Rev 3
1/102
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