74LVX174TTR datasheet, PDF - EEWORLD Datasheet

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74LVX174TTR: DescriptionFlip Flops Hex "D" Flip-Flop; Categorylogic logic; File Size210KB，12 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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74LVX174TTR Overview

Flip Flops Hex "D" Flip-Flop

74LVX174TTR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP16,.25
Contacts	16
Reach Compliance Code	unknown
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
MaximumI(ol)	0.004 A
Humidity sensitivity level	3
Number of digits	6
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	15.5 ns
propagation delay (tpd)	22 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
Trigger type	POSITIVE EDGE
width	4.4 mm
minfmax	95 MHz
Base Number Matches	1

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74LVX174

LOW VOLTAGE CMOS HEX D-TYPE FLIP-FLOP WITH CLEAR

WITH 5V TOLERANT INPUTS

HIGH SPEED:

MAX

= 180MHz (TYP.) at V

= 3.3V

5V TOLERANT INPUTS

INPUT VOLTAGE LEVEL:

=0.8V, V

=2V at V

=3V

LOW POWER DISSIPATION:

= 4

µA

(MAX.) at T

=25°C

LOW NOISE:

OLP

= 0.3V (TYP.) at V

= 3.3V

SYMMETRICAL OUTPUT IMPEDANCE:

| = I

= 4mA (MIN)

BALANCED PROPAGATION DELAYS:

PLH

≅

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 3.6V (1.2V Data Retention)

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 174

IMPROVED LATCH-UP IMMUNITY

SOP

TSSOP

Table 1: Order Codes

PACKAGE

SOP

TSSOP

POWER DOWN PROTECTION ON INPUTS

DESCRIPTION

The 74LVX174 is a low voltage CMOS HEX

D-TYPE FLIP FLOP WITH CLEAR NON

INVERTING fabricated with sub-micron silicon

gate and double-layer metal wiring C

MOS

technology. It is ideal for low power, battery

operated and low noise 3.3V applications.

Figure 1: Pin Connection And IEC Logic Symbols

Information signals applied to D inputs are

transferred to the Q outputs on the positive going

edge of the clock pulse.

When the CLEAR input is held low, the Q outputs

are held low independently of the other inputs.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage.

This device can be used to interface 5V to 3V

system. It combines high speed performance with

the true CMOS low power consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

T&R

74LVX174MTR

74LVX174TTR

August 2004

Rev. 3

1/12

74LVX174TTR Related Products

	74LVX174TTR	74LVX174MTR
Description	Flip Flops Hex "D" Flip-Flop	Flip Flops Hex "D" Flip-Flop
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	STMicroelectronics	STMicroelectronics
Parts packaging code	TSSOP	SOIC
package instruction	TSSOP, TSSOP16,.25	SO-16
Contacts	16	16
Reach Compliance Code	unknown	compliant
series	LV/LV-A/LVX/H	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G16	R-PDSO-G16
JESD-609 code	e4	e4
length	5 mm	9.9 mm
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP
MaximumI(ol)	0.004 A	0.004 A
Humidity sensitivity level	3	3
Number of digits	6	6
Number of functions	1	1
Number of terminals	16	16
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SOP
Encapsulate equivalent code	TSSOP16,.25	SOP16,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE
method of packing	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	15.5 ns	15.5 ns
propagation delay (tpd)	22 ns	22 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.75 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2 V	2 V
Nominal supply voltage (Vsup)	2.7 V	2.7 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	MILITARY	MILITARY
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	1.27 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	40	30
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	4.4 mm	3.9 mm
minfmax	95 MHz	95 MHz
Base Number Matches	1	1

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