Freescale Semiconductor
Technical Data
Document Number: MPC8245ECS02AD
Rev. 3, 12/2005
MPC8245 Hardware Specifications
Addendum for the
MPC8245ARXXnnnx Series
Specifications provided in this document supersede those in
the
MPC8245 Integrated Processor Hardware
Specifications,
Rev. 3 or later, for the part numbers listed in
Table A
only.
Specifications not addressed in this document are
unchanged. Because this document is frequently updated,
refer to http://www.freescale.com or to your Freescale sales
office for the latest version.
Note that headings and table numbers in this document are
not consecutively numbered. They are intended to
correspond to the heading or table affected in the general
hardware specification.
Part numbers addressed in this document are listed in
Table A. For more detailed ordering information, see
Section 9, “Ordering Information.”
Freescale Part Numbers Affected:
MPC8245ARZU400D
MPC8245ARVV400D
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Electrical and Thermal Characteristics
Table A. Part Numbers Addressed in this Data Sheet
Operating Conditions
Freescale
Part No.
1
CPU
Frequency
(MHz)
T
J
(°C)
Significant Differences from
Hardware Specification
Processor
Version
Register
Value
V
DD
MPC8245ARZU400D
MPC8245ARVV400D
400
2.1 ± 100 mV
0 to 85
Modified voltage and temperature
specifications to achieve 400 MHz
0x80811014
Note:
The ‘A’ in the part number represents parts that are manufactured under a 29-angstrom process instead of the original
35-angstrom process. Package Options: ZU - TBGA, V V- Lead Free TBGA
4 Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8245.
4.1.1
Absolute Maximum Ratings
The tables in this section describe the MPC8245 DC electrical characteristics.
Table 1
provides the
absolute maximum ratings.
Table 1. Absolute Maximum Ratings
Characteristic
1
Supply voltage—CPU core and peripheral logic
Supply voltage—memory bus drivers
Supply voltage—PCI and standard I/O buffers
Supply voltage—PLLs
Supply voltage—PCI reference
Input voltage
2
Operational die-junction temperature range
Storage temperature range
Symbol
V
DD
GV
DD
OV
DD
AV
DD
/AV
DD
2
LV
DD
V
in
T
j
T
stg
Range
–0.3 to 2.2
–0.3 to 3.6
–0.3 to 3.6
–0.3 to 2.2
–0.3 to 5.4
–0.3 to 3.6
0 to 85
–55 to 150
Unit
V
V
V
V
V
V
°C
°C
Notes:
1.
Table 2
shows functional and tested operating conditions. Absolute maximum ratings are stress ratings only, and functional
operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
2. PCI inputs with LV
DD
= 5 V ± 5% V DC may undergo corresponding stress at voltages exceeding LV
DD
+ 0.5 V DC.
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
2
Freescale Semiconductor
Electrical and Thermal Characteristics
4.1.2 Recommended Operating Conditions
Table 2
provides the recommended operating conditions for the MPC8245 part numbers described herein.
Table 2. Recommended Operating Conditions
(1)
Recommended
Value for
400 MHz CPU
2.1 V ± 100 mV
2.1 V ± 100 mV
2.1 V ± 100 mV
0 to 85
Characteristic
Symbol
Unit
Supply voltage
CPU PLL supply voltage
PLL supply voltage—peripheral logic
Die-junction temperature
(2)
V
DD
AV
DD
AV
DD
2
T
j
V
V
V
°C
Notes:
1. Freescale tested these operating conditions and recommends them. Proper device operation outside of these conditions is
not guaranteed.
2. For information about the thermal characteristics of this part, refer to the
MPC8245 Integrated Processor Hardware
Specifications.
Note that the lower die-junction temperature creates a greater need to use a heat sink with this part.
4.1.5
Power Characteristics
The AC electrical characteristics and AC timing for the parts described in this document are unaffected,
and comply with the
MPC8245 Integrated Processor Hardware Specifications.
Table 5
provides the power
consumption for the MPC8245 part numbers described herein.
Table 5. Power Consumption
PCI Bus Clock/Memory
Bus Clock
CPU Clock Frequency
(MHz)
66/133/399
Typical
Max—CFP
Max—INT
Doze
Nap
Sleep
2.8
3.3
2.8
1.9
0.7
0.4
W
W
W
W
W
W
1, 5
1, 2
1, 3
1, 4, 6
1, 4, 6
1, 4, 6
Mode
Unit
Notes
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Freescale Semiconductor
3
Electrical and Thermal Characteristics
Table 5. Power Consumption (continued)
PCI Bus Clock/Memory
Bus Clock
CPU Clock Frequency
(MHz)
66/133/399
I/O Power Supplies
10
Mode
Typ—OV
DD
Typ—GV
DD
Range
140–360
340–920
Unit
mW
mW
Notes
7, 8
7, 9
Mode
Unit
Notes
Notes:
1. The values include V
DD
, AV
DD
, and AV
DD
2, but do not include I/O supply power.
2. Maximum—FP power is measured at V
DD
= 2.1 V with dynamic power management enabled while running an entirely
cache-resident, looping, floating point multiplication instruction.
3. Maximum—INT power is measured at V
DD
= 2.1 V with dynamic power management enabled while running entirely
cache-resident, looping, integer instructions.
4. Power saving mode maximums are measured at V
DD
= 2.1 V while the device is in doze, nap, or sleep mode.
5. Typical power is measured at V
DD
= AV
DD
= 2.1 V, OV
DD
= 3.3 V where a nominal FP value, a nominal INT value, and a
value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries to local memory
are averaged.
6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7. The typical minimum I/O power values was the result of the MPC8245 performing cache resident integer operations at the
slowest frequency combination of 33:66:200 (PCI:Mem:CPU) MHz.
8. The typical maximum OV
DD
value resulted from the MPC8245 operating at the fastest frequency combination of 66:133:399
(PCI:Mem:CPU) MHz for the 400-MHz part, and performing continuous flushes of cache lines with alternating ones and
zeros to PCI memory.
9. The typical maximum GV
DD
value resulted from the MPC8245 operating at the fastest frequency combination of
66:133:399 (PCI:Mem:CPU) MHz for the 400-MHz part, and performing continuous flushes of cache lines with alternating
ones and zeros on 64-bit boundaries to local memory.
10. Power consumption of PLL supply pins (AV
DD
and AV
DD
2) < 15 mW that the design guarantees but were not tested.
4.3.1 Clock AC Specifications
Figure 7
through
Figure 10
show the DLL locking range loop delay vs. frequency of operation for
29 angstrom parts. These graphs define the areas of DLL locking for various modes. The gray areas show
where the DLL will lock.
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
4
Freescale Semiconductor
Electrical and Thermal Characteristics
Register settings that define each DLL mode are shown in
Table 9.
Table 9. DLL Mode Definition
DLL Mode
Normal tap delay,
No DLL extend
Normal tap delay,
DLL extend
Max tap delay,
No DLL extend
Max tap delay,
DLL extend
Value of Bit 2 of Config
Register at 0x76
0
Value of Bit 7 of Config
Register at 0x72
0
0
1
1
0
1
1
The DLL_MAX_DELAY bit can lengthen the amount of time through the delay line. This is accomplished
by increasing the time between each of the 128 tap points in the delay line. Although this increased time
makes it easier to guarantee that the reference clock will be within the DLL lock range, it also means there
may be slightly more jitter in the output clock of the DLL, should the phase comparator shift the clock
between adjacent tap points. Refer to Freescale application note AN2164,
MPC8245/MPC8241 Memory
Clock Design Guidelines:Part 1,
for details about DLL modes and memory design.
The value of the current tap point once the DLL has locked can be determined by reading bits 6–0
(DLL_TAP_COUNT) of the DLL tap count register (DTCR, located at offset 0xE3). These bits store the
value (binary 0 through 127) of the current tap point and can indicate whether the DLL advances or
decrements as it maintains the DLL lock. Therefore, for evaluation purposes, DTCR can be read for all
DLL modes that support the T
loop
value that is used for the trace length of SDRAM_SYNC_OUT to
SDRAM_SYNC_IN. The DLL mode that provides the smallest tap point value seen in DTCR should be
used. This is because the bigger the tap point value, the more jitter that can be expected for clock signals.
Note that keeping a DLL mode that is locked below tap point 12 is not recommended.
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Freescale Semiconductor
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