LP3986TLX-2818/NOPB datasheet, PDF

Datasheet> All Categories > Power/power management> The power supply circuit> LP3986TLX-2818/NOPB

LP3986TLX-2818/NOPB: DescriptionLDO Voltage Regulators Dual Micropower 150 mA Ultra Low-Dropout CMOS Voltage Regulators in micro SMD Package 8-DSBGA; CategoryPower/power management The power supply circuit; File Size1012KB，18 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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LP3986TLX-2818/NOPB Overview

LDO Voltage Regulators Dual Micropower 150 mA Ultra Low-Dropout CMOS Voltage Regulators in micro SMD Package 8-DSBGA

LP3986TLX-2818/NOPB Parametric

Parameter Name	Attribute value
Brand Name	Texas Instruments
Is it lead-free?	Contains lead
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	BGA
package instruction	VFBGA, BGA8,3X3,20
Contacts	8
Reach Compliance Code	compliant
ECCN code	EAR99
Adjustability	FIXED
Maximum drop-back voltage 1	0.1 V
Nominal dropback voltage 1	0.06 V
Maximum drop-back voltage 2	0.1 V
Maximum absolute input voltage	6.5 V
Maximum input voltage	6 V
Minimum input voltage	2.7 V
JESD-30 code	S-PBGA-B8
JESD-609 code	e1
length	1.56 mm
Maximum grid adjustment rate	0.0097%
Maximum load regulation	0.0417%
Humidity sensitivity level	1
Number of functions	1
Output times	2
Number of terminals	8
Working temperatureTJ-Max	125 °C
Working temperature TJ-Min	-40 °C
Maximum output current 1	0.15 A
Maximum output current 2	0.15 A
Maximum output voltage 1	2.884 V
Minimum output voltage 1	2.716 V
Nominal output voltage 1	2.8 V
Maximum output voltage 2	1.854 V
Minimum output voltage 2	1.746 V
Nominal output voltage 2	1.8 V
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA8,3X3,20
Package shape	SQUARE
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Regulator type	FIXED POSITIVE MULTIPLE OUTPUT LDO REGULATOR
Maximum seat height	0.675 mm
surface mount	YES
technology	CMOS
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
Maximum voltage tolerance	3%
width	1.56 mm

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