IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
CMOS StaticRAM
16K (4K x 4-BIT)
CACHE-TAG RAM
Integrated Device Technology, Inc.
IDT6178S
FEATURES:
• High-speed Address to MATCH Valid time
– Military: 12/15/20/25ns
– Commercial: 10/12/15/20/25ns (max.)
• High-speed Address Access time
– Military: 12/15/20/25ns
– Commercial: 10/12/15/20/25ns (max.)
• Low-power consumption
– IDT6178S
Active: 300mW (typ.)
• Produced with advanced CMOS high-performance
technology
• Input and output TTL-compatible
• Standard 22-pin Plastic or Ceramic DIP, 24-pin SOJ
• Military product 100% compliant to MIL-STD-883,
Class B
DESCRIPTION:
The IDT6178 is a high-speed cache address comparator
sub-system consisting of a 16,384-bit StaticRAM organized
as 4K x 4. Cycle Time and Address to MATCH Valid are equal.
The IDT6178 features an onboard 4-bit comparator that
compares RAM contents and current input data. The result is
an active HIGH on the MATCH pin. The MATCH pins of
several IDT6178s can be handed together to provide enabling
or acknowledging signals to the data cache or processor.
The IDT6178 is fabricated using IDT’s high-performance,
high-reliability CMOS technology. Address to MATCH and
Data to MATCH times are as fast as 10ns.
All inputs and outputs of the IDT6178 are TTL-compatible
and the device operates from a single 5V supply.
The IDT6178 is packaged in either a 22-pin, 300-mil Plastic
or Ceramic DIP package or 24-pin SOJ. Military grade product
is manufactured in compliance with latest revision of MIL-
STD-883, Class B, making it ideally suited to military tempera-
ture applications demanding the highest level of performance
and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
0
ADDRESS
DECODE
A
11
16,384-BIT
MEMORY
ARRAY
V
CC
GND
I/O
0
– I/O
3
4
CONTROL I/O
4
WE
OE
CLR
CONTROL
CLEAR
MEMORY
ARRAY
4
COMPARATOR
4
MATCH
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2953 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1994
Integrated Device Technology, Inc.
MAY 1994
DSC-1059/2
11.1
11.1
1
1
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
1
2
3
4
5
6
7
8
9
10
11
DIP
TOP VIEW
A
0
1
2
3
4
5
6
7
8
9
10
11
12
SOJ
TOP VIEW
24
23
22
21
20
S024-4
19
18
17
16
15
14
13
V
CC
A
11
A
10
A
9
A
8
NC
22
21
20
19
P22-1
&
D22-1
18
17
16
15
14
13
12
V
CC
A
11
A
10
A
9
A
8
A
1
A
2
A
3
A
4
A
5
NC
A
6
A
7
CLR
I/O
3
I/O
2
I/O
1
I/O
0
MATCH
2953 drw 02
CLR
I/O
3
I/O
2
I/O
1
I/O
0
MATCH
2953 drw 03
OE
WE
GND
OE
WE
GND
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Terminal Voltage with respect
to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–0.5 to +7.0
–55 to +125
–65 to +135
–65 to +150
1.0
50
Unit
V
°C
°C
°C
W
mA
PIN DESCRIPTIONS
A
0
–A
11
I/O
0
–I/O
3
MATCH
Address Inputs
Data Input/Output
Match
Write Enable
Output Enable
Clear
Power
Ground
2953 tbl 01
T
A
T
BIAS
T
STG
P
T
I
OUT
WE
OE
CLR
V
CC
GND
2953 tbl 04
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Military
Ambient Temperature
0°C to +70°C
–55°C to +125°C
GND
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
2953 tbl 02
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
(2)
–0.5
(1)
Typ.
5.0
0
–
–
Max.
5.5
0
6.0
0.8
Unit
V
V
V
V
2953 tbl 05
TRUTH TABLES
(1)
NOTES:
1. V
IL
= –3.0V for pulse width less than 20ns, once per cycle.
2. V
IH
= 2.5V for clear pin.
WE
H
L
H
X
OE
H
X
L
X
CLR
H
H
H
L
MATCH
Valid
(2)
Invalid
Invalid
Invalid
Mode
Match Cycle
Write Cycle
Read Cycle
Clear Cycle
2953 tbl 03
CAPACITANCE
(T
A
= 25°C, f = 1MHz)
Symbol
C
IN
C
I/O
Parameter
Input Capacitance
I/O Capacitance
Condition
V
IN
= 0V
V
OUT
= 0V
Max
8
8
Units
pF
pF
NOTE:
1. H = V
IH
, L = V
IL
, X = Don’t care.
2. Valid Match = V
OH
, Valid Non-Match = V
OL.
NOTE:
2953 tbl 06
1. This parameter is determined by device characterization, but is not
production tested.
11.1
2
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
6178S
Symbol
|I
LI
|
|I
LO
|
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Condition
V
CC
= 5.5V, V
IN
= 0V to V
CC
Min.
—
—
—
—
—
—
2.4
2.4
Max.
10
10
0.4
0.5
0.4
0.5
—
—
Unit
µA
µA
V
V
V
V
V
V
2953 tbl 07
OE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 8mA (I/O
0
– I/O
3
)
I
OL
= 10mA (I/O
0
– I/O
3
)
I
OL
= 16mA (Match)
I
OL
= 20mA (Match)
V
OH
Output High Voltage
I
OH
= –4mA (I/O
0
– I/O
3
)
I
OH
= –8mA (Match)
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
Symbol
I
CC1
I
CC2
Parameter
Operating Power Supply Current
Outputs Open, V
CC
= Max., f = 0
(2)
COM'L.
MIL.
6178S10
Max.
90
—
180
—
6178S12
(1)
Max.
90
110
160
180
6178S15
(1)
Max.
90
110
140
160
6178S20/25
Max.
90
110
140
160
Unit
mA
mA
mA
mA
2953 tbl 08
Dynamic Operating Current
COM'L.
(2)
Outputs Open, V
CC
= Max., f = f
MAX
MIL.
NOTES:
1. Military values are preliminary only.
2. f
MAX
= 1/t
RC
, only address inputs are cycling at f
MAX
. f = 0 means no address inputs change.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
AC Test Load for Match Cycle
GND to 3.0V
5ns
1.5V
1.5V
See Figures 2 and 3
See Figure 1
2953 tbl 09
+5V
240
Ω
MATCH
OUT
128
Ω
30pF*
2953 drw 04
Figure 1. AC Test Load for MATCH
+5V
+5V
480
Ω
DATA
OUT
255
Ω
30pF*
DATA
OUT
255
Ω
480
Ω
5pF*
2953 drw 05
2953 drw 06
Figure 2. AC Test Load
Figure 3. AC Test Load
(for t
OLZ
, t
OHZ
, t
WHZ
, t
OW
)
* Including scope and jig.
11.1
3
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
CYCLE DESCRIPTION
Match Cycle:
A match cycle occurs when all control signals
(
OE
,
WE
,
CLR
) are HIGH. At that time, data supplied to the
RAM on the I/O pins is compared with the data stored at the
specified address. The totem-pole match output is HIGH
when there is a match at all data bits, and drives LOW if there
is not a match.
Write Cycle:
The write cycle is conventional, occuring when
WE
is LOW and
CLR
is HIGH.
OE
may be either HIGH or LOW,
since it is overridden by
WE
. The state of the Match pin is not
guaranteed, but in the current implementation it continues to
reflect the output of the comparator. The Match pin goes
HIGH during write cycles since the data at the specified
address is the same as the data (being written) at the I/Os of
the RAM.
6178S10
(1)
Symbol
Match Cycle
t
ADM
t
DAM
t
MHO
t
OEM
t
MHW
t
WEM
t
MHCLR
t
MHA
t
MHD
Address to Match Valid
Data Input to Match Valid
Match Valid Hold from
OE
—
—
0
—
0
—
0
3
3
10
8
—
10
—
10
—
—
—
Parameter
Min.
Max.
Read Cycle:
When
WE
and
CLR
are HIGH and
OE
is LOW,
the RAM is in a read cycle. The state of the Match pin is not
guaranteed, but in the current implementation it continues to
reflect the output of the comparator. The Match pin goes
HIGH during read cycles since the data at the specified
address is the same as the data (being read) at the I/Os of the
RAM.
Clear Cycle:
When
CLR
is asserted, every bit in the RAM is
cleared to zero. If
OE
is LOW during a clear cycle, the RAM
I/Os will be driven. However, this data is not necessarily
zeros, even after a considerable time. The Match pin is
enabled, but its state is not predicable.
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
6178S12
Min.
—
—
0
—
0
—
0
3
3
Max.
12
11
—
12
—
12
—
—
—
6178S15
Min.
—
—
0
—
0
—
0
3
3
Max.
15
13
—
15
—
15
—
—
—
6178S20
Min.
—
—
0
—
0
—
0
3
3
Max.
20
15
—
20
—
20
—
—
—
6178S25
Min.
—
—
0
—
0
—
0
3
3
Max.
25
15
—
20
—
20
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2953 tbl 10
OE
HIGH to Match Valid
Match Valid Hold from
WE
WE
HIGH to Match Valid
Match Valid Hold from
CLR
Match Valid Hold from Address
Match Valid Hold from Data
NOTE:
1. 0°C to +70°C temperature range only.
TIMING WAVEFORM OF MATCH CYCLE
(1)
ADDRESS
t
ADM
t
MHA
OE
t
OEM
t
MHO
WE
t
WEM
t
MHW
CLR
t
MHCLR
I/O
1–4
VALID READ DATA
OUT
VALID MATCH DATA
IN
t
DAM
MATCH
NO MATCH
MATCH
t
MHD
MATCH VALID
MATCH
2953 drw 07
NOTE:
1. It is not recommended to let address and data input pins float while MATCH pin is active.
11.1
4
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
6178S10
(1)
Symbol
Read Cycle
t
RC
t
AA
t
OE
t
OH
t
OLZ
(2)
t
OHZ
(2)
Read Cycle Time
Address Access Time
Output Enable Access Time
Output Hold from Address Change
Output Enable to Output in Low-Z Time
Output Disable to Output in High-Z Time
10
—
—
3
2
—
—
10
7
—
—
6
12
—
—
3
2
—
—
12
8
—
—
7
15
—
—
3
2
—
—
15
10
—
—
9
20/25
—
—
3
2
—
—
20/25
15
—
—
12
ns
ns
ns
ns
ns
ns
2953 tbl 11
6178S12
Min.
Max.
6178S15
Min.
Max.
6178S20/25
Min.
Max.
Unit
Parameter
Min.
Max.
NOTES:
1. 0°C to +70°C temperature range only.
2. This parameter guaranteed with AC load (Figure 3) by device characterization, but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
t
OH
OE
t
OLZ
DATA
OUT
(3)
t
OE
t
OHZ (3)
DATA
OUT
VALID
2953 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 2
(1,2)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
DATA
OUT
VALID
2953 drw 09
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Output enable is continuously active,
OE
is LOW.
3. Transition is measured
±200V
from steady state.
11.1
5
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