HSP50215 datasheet, PDF - EEWORLD Datasheet

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HSP50215: DescriptionSPECIALTY TELECOM CIRCUIT, PQFP100; Categorysemiconductor Analog mixed-signal IC; File Size163KB，21 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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SPECIALTY TELECOM CIRCUIT, PQFP100

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HSP50215

Data Sheet

January 1999

File Number

4346.4

Digital UpConverter

The HSP50215 Digital UpConverter (DUC) is a QASK/FM

modulator/FDM upconverter designed for high dynamic range

applications such as cellular basestations. The DUC combines

shaping and interpolation filters, a complex modulator, and

Timing and Carrier NCO’s into a single package. Each DUC

can create a single FDM channel. Multiple DUC’s can be

cascaded digitally for multi-channel applications.

The HSP50215 supports both vector and FM modulation. In

vector modulation mode, the DUC accepts 16-bit I and Q

samples to generate virtually any quadrature AM or PM

modulation format. The DUC also has two FM modulation

modes. In the FM with pulse shaping mode, the 16-bit

frequency samples are pulse shaped/bandlimited prior to FM

modulation. No bandlimiting filter follows the FM modulator.

This FM mode is useful for GMSK type modulation formats. In

the FM with bandlimiting filter mode, the 16-bit frequency

samples directly drive the FM modulator. The FM modulator

output is filtered to limit the spectral occupancy. This FM mode

is useful for analog FM or FSK modulation formats.

The DUC includes an NCO driven interpolation ﬁlter, which

allows the input and output sample rate to have a non-

integer or variable relationship. This re-sampling feature

simpliﬁes cascading modulators with sample rates that do

not have harmonic or integer frequency relationships.

The DUC offers digital output spectral purity that exceeds

85dB at the maximum output sample rate of 52 MSPS, for

input sample rates as high as 300 KSPS.

A 16-bit microprocessor compatible interface is used to load

configuration and baseband data. A programmable FIFO depth

interrupt simplifies the interface to the I and Q input FIFOs.

Features

• Output Sample Rates Up to 52 MSPS (48 MSPS

Industrial); Input Data Rates Up to 3.25 MSPS

• I/Q Vector, FM, and Shaped FM Modulation Formats

• 32-Bit Programmable Carrier NCO; 30-Bit Programmable

Symbol Timing NCO

• Programmable I and Q, 256 Tap, Shaping FIR Filters with

Interpolation by 4, 8 or 16

• Interpolation Filter Up Samples Shaping Filter Output to

Output Sample Rate Under NCO Control

• Processing Capable of >90dB SFDR

• Cascade Input for Multiple Channel Transmissions

• 16-Bit

µProcessor

Interface for Conﬁguration and User

Data Input

Applications

• Single or Multiple Channel Digital Software Radio

Transmitters (Wide-Band or Narrow-Band)

• Base Station Transceivers

• Operates with HSP50214 in Software Radio Solutions

• Compatible with the HI5741 D/A Converter

• HSP50215EVAL Evaluation Board Available

Ordering Information

PART

NUMBER

HSP50215VC

HSP50215VI

TEMP

RANGE (

0 to 70

-40 to 85

PACKAGE

100 Ld MQFP

PKG. NO

Q100 .14x20

s100 Ld MQFP Q100 .14x20

Block Diagram

†

µP

CONTROL SIGNALS

OUTPUT FORMATTER

CAS(15:0)

CASZ

IIN(15:0)

QIN(15:0)

1-7 DEEP

FIFO

†

QFIFO

MUX

GAIN

CTRL

MUX

LIMITER

IFIFO

SHAPING FILTER

INTERPOLATION

FILTER

OUT(15:0)

MUX

REFCLK

SYNCIN

MOD

Q FM

RST

C(15:0)

A(9:0)

CONTROL

QIN(15:0)

†

IIN(15:0)

†

CF(31:0)

†

SF(29:0)

†

COS

SIN

I FM

OFM

NCO

CF(31:0)

NCO

†

SYNCOUT

FIFORDY

SAMPCLK

3-422

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

HSP50215

Pin Descriptions

NAME

GND

C(15:0)

TYPE

I/O

+5V Power supply input.

Power supply ground input.

µP

Bidirectional Data bus. The C(15:0) bus is used for loading the conﬁguration data and sample vectors for mod-

ulation. C15 is the MSB.

µP

Address Bus. The A(9:0) bus is used for addressing the proper registers for loading the conﬁguration data and

sample vectors for modulation. A9 is the MSB.

µP

Write Strobe. When CE is asserted, data on the C(15:0) data bus is loaded into the address location found on

the A(9:0) bus on the rising edge of the WR signal. In some cases, there is an internal synchronization to the master

clock that must be completed before the next data is written. See the

µP

interface section for more information.

µP

Read Control. When RD and CE are low, the data found in the address location deﬁned by A(9:0) is routed to

the C(15:0)

µP

data bus on the next rising edge of REFCLK.

µP

Chip Enable. Used to gate the WR and RD

µP

interface control signals.

FIFO Ready. A FIFORDY assertion indicates that the I and Q FIFOs have reached the programmed FIFO depth and

more samples are required to maintain that FIFO depth.

Reference Clock. REFCLK is the master clock for the DUC. All timing is relative to the REFCLK rising edge. The

frequency of the reference clock is denoted f

CLK

, and is the rate at which data is output from the part.

Cascade Input Bus. This input bus is used to cascade multiple parts by routing the digital modulated signal from

one DUC into the output summer of a second DUC. CAS(15:0) is 2’s complement format and is sampled on the

rising edge of REFCLK. CAS15 is the MSB.

Cascade Input Bus Zero. When CASZ is asserted (pulled high), the part places zeroes on the CAS(15:0) data path.

CASZ is asynchronous (not registered) to REFCLK and should not be changed on the ﬂy. When unused, pull high

with a pull up resistor (~22kΩ).

Output Data Bus. OUT(15:0) contains the digital modulated DUC output samples and is updated on the rising edge

of the REFCLK. OUT15 is the MSB.

Output Data Bus Format. When OFM is asserted (pulled high), the output bus format is 2’s complement. When not

asserted, the output format is offset binary. The OFM input is asynchronous (not registered) to REFCLK and should

not be changed on the ﬂy.

Output Data Bus Enable. When OE is asserted (dropped low), the output data bus OUT(15:0) is enabled. When OE

is not asserted (pulled high), the output data bus OUT(15:0) is placed in the high impedance state.

Sync Input. The SYNCIN input is used to synchronize the processing of multiple parts. The SYNCOUT of one part

acts as a master and is connected to the SYNCIN of all of the DUC’s that are to by synchronized. The DUC can be

programmed so that either rising or falling edge of this signal initiates the processing.

Sync Output. The SYNCOUT output is used to synchronize the processing of multiple parts. The SYNCOUT of one

part acts as a master, and is connected to the SYNCIN of all of the DUC’s that are to be synchronized.

Sample Clock. This clock is provided to the data source to indicate when data is being transferred from the FIFO to

the shaping ﬁlter. The SAMPCLK output is generated by the sample rate NCO when the digital ﬁlter takes a new

sample. It has approximately 50% duty cycle. The sample is taken on the high-to-low transition. SAMPCLK may be

used instead of FIFORDY.

Reset. When the RST input is asserted (dropped low), the DUC is reset and all processing halts. The DUC may

also be reset on

µP

command. Processing remains halted until a sync is generated either by

µP

command or

assertion of SYNCIN. See the Reset section details of the specific functions halted by this control signal.

DESCRIPTION

A(9:0)

FIFORDY

REFCLK

CAS(15:0)

CASZ

OUT(15:0)

OFM

SYNCIN

SYNCOUT

SAMPCLK

RST

3-425

HSP50215 Related Products

	HSP50215	HSP50215VC	HSP50215VI
Description	SPECIALTY TELECOM CIRCUIT, PQFP100	SPECIALTY TELECOM CIRCUIT, PQFP100	SPECIALTY TELECOM CIRCUIT, PQFP100

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