Military & Space Products
HLX6228
128K x 8 STATIC RAM—Low Power SOI
FEATURES
RADIATION
• Fabricated with RICMOS
™
IV Silicon on Insulator
(SOI) 0.7
µm
Low Power Process (L
eff
= 0.55
µm)
• Total Dose Hardness through 1x10
6
rad(Si)
• Neutron Hardness through 1x10
14
cm
-2
• Dynamic and Static Transient Upset Hardness
through 1x10
9
rad(Si)/s
• Dose Rate Survivability through 1x10
11
rad(Si)/s
• Soft Error Rate of <1x10
-10
Upsets/bit-day in Geosyn-
chronous Orbit
• No Latchup
OTHER
• Read/Write Cycle Times
≤
32 ns (-55 to 125°C)
• Typical Operating Power <9 mW/MHz
• JEDEC Standard Low Voltage
CMOS Compatible I/O
• Single 3.3 V
±
0.3 V Power Supply
• Asynchronous Operation
• Packaging Options
– 32-Lead CFP (0.820 in. x 0.600 in.)
– 40-Lead CFP (0.775 in. x 0.710 in.)
GENERAL DESCRIPTION
The 128K x 8 Radiation Hardened Static RAM is a high
performance 131,072 word x 8-bit static random access
memory with industry-standard functionality. It is fabricated
with Honeywell’s radiation hardened technology, and is
designed for use in low voltage systems operating in radiation
environments. The RAM operates over the full military
temperature range and requires only a single 3.3 V
±
0.3V
power supply. The RAM is compatible with JEDEC standard
low voltage CMOS I/O. Power consumption is typically less
than 9 mW/MHz in operation, and less than 2 mW when de-
selected. The RAM read operation is fully asynchronous, with
an associated typical access time of 32 ns at 3.3 V.
Honeywell’s enhanced SOI RICMOS™ IV (Radiation Insensi-
tive CMOS) technology is radiation hardened through the use
of advanced and proprietary design, layout and process
hardening techniques.The RICMOS™ IV low power process is
a SIMOX CMOS technology with a 150 Å gate oxide and a
minimum drawn feature size of 0.7
µm
(0.55
µm
effective gate
length—L
eff
). Additional features include tungsten via plugs,
Honeywell’s proprietary SHARP planarization process and a
lightly doped drain (LDD) structure for improved short channel
reliability. A 7 transistor (7T) memory cell is used for superior
single event upset hardening, while three layer metal power
bussing and the low collection volume SIMOX substrate
provide improved dose rate hardening.
Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 323-8295 • http://www.myspaceparts.com
HLX6228
FUNCTIONAL DIAGRAM
•
•
•
A:3-7,12,14-16
9
Row
Decoder
131,072 x 8
Memory
Array
•
•
•
CE
NCS
Column Decoder
Data Input/Output
NWE
WE • CS • CE
8
8
DQ:0-7
NOE
NWE • CS • CE • OE
(0 = high Z)
Signal
1 = enabled
#
Signal
A:0-2, 8-11, 13
8
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
SIGNAL DEFINITIONS
A: 0-16
DQ: 0-7
NCS
Address input pins which select a particular eight-bit word within the memory array.
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers except CE. This part must be Read and Write controlled using the NCS pin: it
requires that NCS returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse
to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched.
The part must be controlled in this fashion to meet the timing specifications defined.
Negative write enable, when at a low level activates a write operation and holds the data output drivers in
a high impedance state. When at a high level NWE allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
NWE
NOE
CE
TRUTH TABLE
NCS
L
L
H
X
CE
H
H
X
L
NWE
H
L
XX
XX
NOE
L
X
XX
XX
MODE
Read
Write
Deselected
Disabled
DQ
Data Out
Data In
High Z
High Z
Notes:
X: VI=VIH or VIL
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained
for NCS=X, CE=X, NWE=X
2
HLX6228
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
after the specified total ionizing radiation dose. All electri-
cal and timing performance parameters will remain within
specifications after rebound at VDD = 3.6 V and T =125°C
extrapolated to ten years of operation. Total dose hard-
ness is assured by wafer level testing of process monitor
transistors and RAM product using 10 KeV X-ray and Co60
radiation sources. Transistor gate threshold shift correla-
tions have been made between 10 KeV X-rays applied at
a dose rate of 1x10
5
rad(Si)/min at T = 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
The SRAM will meet any functional or electrical specifica-
tion after exposure to a radiation pulse up to the transient
dose rate survivability specification, when applied under
recommended operating conditions. Note that the current
conducted during the pulse by the RAM inputs, outputs,
and power supply may significantly exceed the normal
operating levels. The application design must accommo-
date these effects.
Neutron Radiation
The SRAM will meet any functional or timing specification
after exposure to the specified neutron fluence under
recommended operating or storage conditions. This as-
sumes an equivalent neutron energy of 1 MeV.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse, up to the specified transient
dose rate upset specification, when applied under rec-
ommended operating conditions. To ensure validity of all
specified performance parameters before, during, and
after radiation (timing degradation during transient pulse
radiation (timing degradation during transient pulse ra-
diation is
≤10%),
it is suggested that stiffening capaci-
tance be placed on or near the package VDD and VSS,
with a maximum inductance between the package (chip)
and stiffening capacitance of 0.7 nH per part. If there are
no operate-through or valid stored data requirements,
typical circuit board mounted de-coupling capacitors are
recommended.
Soft Error Rate
The SRAM is capable of meeting the specified Soft Error
Rate (SER), under recommended operating conditions.
This hardness level is defined by the Adams 90% worst
case cosmic ray environment for geosynchronous orbits.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under recom-
mended operating conditions. Fabrication with the
SIMOX substrate material provides oxide isolation be-
tween adjacent PMOS and NMOS transistors and elimi-
nates any potential SCR latchup structures. Sufficient
transistor body tie connections to the p- and n-channel
substrates are made to ensure no source/drain snapback
occurs.
RADIATION HARDNESS RATINGS (1)
Parameter
Total Dose
Transient Dose Rate Upset
Transient Dose Rate Survivability
Soft Error Rate
Neutron Fluence
Limits (2)
≥1x10
6
≥1x10
9
≥1x10
11
<1x10
-10
≥1x10
14
Units
rad(Si)
rad(Si)/s
rad(Si)/s
upsets/bit-day
N/cm
2
Test Conditions
T
A
=25°C
Pulse width
≤1 µs
Pulse width
≤50
ns, X-ray,
VDD=4.0 V, T
A
=25°C
T
A
=125°C, Adams 90%
worst case environment
1 MeV equivalent energy,
Unbiased, T
A
=25°C
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=3.0 V to 3.6 V, TA=-55°C to 125°C.
3
HLX6228
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Symbol
VDD
VPIN
TSTORE
TSOLDER
PD
IOUT
VPROT
Parameter
Supply Voltage Range (2)
Voltage on Any Pin (2)
Storage Temperature (Zero Bias)
Soldering Temperature (5 Seconds)
Maximum Power Dissipation (3)
DC or Average Output Current
ESD Input Protection Voltage (4)
Thermal Resistance (Jct-to-Case)
Junction Temperature
32 FP
40 FP
2000
2
2
175
Min
-0.5
-0.5
-65
Max
6.0
VDD+0.5
150
270
2
25
Units
V
V
°C
°C
W
mA
V
°C/W
°C
Θ
JC
TJ
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description
Symbol
VDD
TA
VPIN
Parameter
Supply Voltage (referenced to VSS)
Ambient Temperature
Voltage on Any Pin (referenced to VSS)
Min
3.0
-55
-0.3
Typ
3.3
25
Max
3.6
125
VDD+0.3
Units
V
°C
V
CAPACITANCE
(1)
Symbol
CI
CO
Parameter
Input Capacitance
Output Capacitance
Typical
(1)
Worst Case
Min
Max
7
9
Units
pF
pF
Test Conditions
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
DATA RETENTION CHARACTERISTICS
Symbol
VDR
IDR
Parameter
Data Retention Voltage
Data Retention Current
Typical
(1)
Worst Case
(2)
Units
Min
2.5
700
Max
V
µA
NCS=VDR
VI=VDR or VSS
NCS=VDD=VDR
VI=VDR or VSS
Test Conditions
(1) Typical operating conditions: TA= 25°C, pre-radiation.
(2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C.
4
HLX6228
DC ELECTRICAL CHARACTERISTICS
Worst Case
(2)
Symbol
Parameter
Typ
(1)
Min
IDDSB1
Static Supply Current
Max
700
700
3.2
2.2
-5
-10
5
10
.275xV
DD
.725xV
DD
0.4
2.7
µA
µA
mA
mA
µA
µA
V
V
V
V
VIH=VDD IO=0
VIL=VSS Inputs Stable
NCS=VDD, CE=VSS, IO=0,
f=40 MHz
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
VSS VI VDD
VSS VIO VDD, Output=High Z
March Pattern VDD = 3.0V
March Pattern VDD = 3.6V
VDD = 3.0V, IOL = 8 mA
VDD = 3.0V, IOH = -4 mA
Units Test Conditions
IDDSBMF Standby Supply Current – Deselected/Disabled
IDDOPW
IDDOPR
II
IOZ
VIL
VIH
VOL
VOH
Dynamic Supply Current, Selected (Write)
Dynamic Supply Current, Selected (Read)
Input Leakage Current
Output Leakage Current
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Voltage
High-Level Output Voltage
(1) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55°C to +125°C, post total dose at 25°C.
(3) All inputs switching. DC average current.
2.2 V
Vref1
249Ω
DUT
output
Vref2
+
-
Valid high
output
+
-
Valid low
output
CL >50 pF*
*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
Tester Equivalent Load Circuit
5
FPGA/CPLD
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