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M5-256/74-5YC

Description
EE PLD, 7.5 ns, PQFP100
Categorysemiconductor    Programmable logic devices   
File Size536KB,47 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Download Datasheet Parametric View All

M5-256/74-5YC Overview

EE PLD, 7.5 ns, PQFP100

M5-256/74-5YC Parametric

Parameter NameAttribute value
Number of input and output buses74
Number of terminals100
Minimum operating temperature0.0 Cel
Maximum operating temperature70 Cel
stateTransferred
Programmable logic typeEE PLD
clock_frequency_max71.4 MHz
in_system_programmableYES
jesd_30_codeS-PQFP-G100
jtag_bsYES
Dedicated input quantity0.0
umber_of_macro_cells128
organize0 DEDICATED INPUTS, 74 I/O
Output functionMACROCELL
Packaging MaterialsPLASTIC/EPOXY
ckage_codeQFP
ckage_equivalence_codeQFP100,.63SQ,20
packaging shapeSQUARE
Package SizeFLATPACK
wer_supplies3.3
gation_delay7.5 ns
qualification_statusCOMMERCIAL
sub_categoryProgrammable Logic Devices
Rated supply voltage3.3 V
Minimum supply voltage3 V
Maximum supply voltage3.6 V
surface mountYES
CraftsmanshipCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal spacing0.5000 mm
Terminal locationQUAD
dditional_feature128 MACROCELLS
MACH 5 CPLD Family
Fifth Generation MACH Architecture
FEATURES
x
High logic densities and I/Os for increased logic integration
x
x
x
x
x
x
x
— 128 to 512 macrocell densities
— 68 to 256 I/Os
Wide selection of density and I/O combinations to support most application needs
— 6 macrocell density options
— 7 I/O options
— Up to 4 I/O options per macrocell density
— Up to 5 density & I/O options for each package
Performance features to fit system needs
— 5.5 ns t
PD
Commercial, 7.5 ns t
PD
Industrial
— 182 MHz f
CNT
— Four programmable power/speed settings per block
Flexible architecture facilitates logic design
— Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
— Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— IEEE 1149.1 compliant for boundary scan testing
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Por
— PCI compliant (-5/-6/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system design
— Bus-Friendly™ Inputs & I/Os
— Individual output slew rate control
— Hot socketing
— Programmable security bit
Advanced E
2
CMOS process provides high performance, cost effective solutions
Supported by ispDesignEXPERT™ software for rapid logic development
— Supports HDL design methodologies with results optimized for MACH 5 devices
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Lattice and Third-party hardware programming support
— LatticePRO™ software for in-system programmability support on PCs and Automat
Equipment
— Programming support on all major programmers including Data I/O, BP Microsystem
and System General
Publication#
20446
Amendment/
0
Rev:
I
Issue Date:
September 2000
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