M74HCT165 datasheet, PDF - EEWORLD Datasheet

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M74HCT165: Description8 BIT PISO SHIFT REGISTER; File Size262KB，13 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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M74HCT165 Overview

8 BIT PISO SHIFT REGISTER

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M54HCT165

M74HCT165

8 BIT PISO SHIFT REGISTER

HIGH SPEED

= 17 ns (TYP.) AT V

= 5 V

LOW POWER DISSIPATION

= 4

µA

(MAX.) AT T

= 25

°C

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

BALANCED PROPAGATION DELAYS

PLH

= t

PHL

SYMMETRICAL OUTPUT IMPEDANCE

I



= 4 mA (MIN.)

COMPATIBLE WITH TTL OUTPUTS

= 2 V (MIN.) V

= 0.8 V (MAX.)

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS165

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

DESCRIPTION

The M54/74HCT165 is a high speed CMOS 8 BIT

PISO SHIFT REGISTER fabricated in silicon gate

MOS technology. It has the same high speed

performance of LSTTL combined with true CMOS

low power consumption. It achives the high speed

operation similar to equivalent LSTTL while

maintaining the CMOS low power dissipation.

This device contains eight clocked master slave RS

flip-flops connected as a shift register, with auxiliary

gating to provide over-riding asynchronous parallel

entry. Parallel data entrens when the shift/load input

is low. The parallel data can change while shift/load

is low, provided that the recommended set-up and

hold times are observed. For clocked operation,

shift/load must be high. The two clock input perform

identically; one can be used as a clock inhibit by

applying a high signal; to permit this operation

clocking is accomplished through a 2 input nor

gates.

To avoid double clocking, however, the inhibit signal

should only go high while the clock is high.

Otherwise the rising inhibit signal will cause the

same response as rising clock edge.This integrated

circuit has input and output characteristics that are

fully compatible with 54/74 LSTTL logic families.

M54/74HCT devices are designed to directly

interface HSCMOS systems with TTL and NMOS

components. They are also plug in replacements for

LSTTL devices giving a reduction of power

consumption. All inputs are equipped with

protection circuits against static discharge and

transient excess voltage.

October 1993

ORDER CODES :

M54HCT165F1R

M74HCT165M1R

M74HCT165B1R

M74HCT165C1R

PIN CONNECTIONS

(top view)

NC =

No Internal

Connection

1/13

M74HCT165 Related Products

	M74HCT165	M74HCT165B1R	M74HCT165M1R	M74HCT165C1R	M54HCT165	M54HCT165F1R
Description	8 BIT PISO SHIFT REGISTER	8 BIT PISO SHIFT REGISTER	8 BIT PISO SHIFT REGISTER	8 BIT PISO SHIFT REGISTER	8 BIT PISO SHIFT REGISTER	8 BIT PISO SHIFT REGISTER
Is it Rohs certified?	-	conform to	conform to	conform to	-	incompatible
Parts packaging code	-	DIP	SOIC	QFN	-	DIP
package instruction	-	PLASTIC, DIP-16	SOP, SOP16,.25	CC-20	-	DIP, DIP16,.3
Contacts	-	16	16	20	-	16
Reach Compliance Code	-	compli	compli	compli	-	_compli
Other features	-	CLOCK INHIBIT	CLOCK INHIBIT	CLOCK INHIBIT	-	CLOCK INHIBIT
Counting direction	-	RIGHT	RIGHT	RIGHT	-	RIGHT
series	-	HCT	HCT	HCT	-	HCT
JESD-30 code	-	R-PDIP-T16	R-PDSO-G16	S-PQCC-J20	-	R-GDIP-T16
JESD-609 code	-	e3	e4	e3	-	e0
Load capacitance (CL)	-	50 pF	50 pF	50 pF	-	50 pF
Logic integrated circuit type	-	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	-	PARALLEL IN SERIAL OUT
Number of digits	-	8	8	8	-	8
Number of functions	-	1	1	1	-	1
Number of terminals	-	16	16	20	-	16
Maximum operating temperature	-	125 °C	125 °C	85 °C	-	125 °C
Minimum operating temperature	-	-55 °C	-55 °C	-40 °C	-	-55 °C
Output polarity	-	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	-	COMPLEMENTARY
Package body material	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	CERAMIC, GLASS-SEALED
encapsulated code	-	DIP	SOP	QCCJ	-	DIP
Encapsulate equivalent code	-	DIP16,.3	SOP16,.25	LDCC20,.4SQ	-	DIP16,.3
Package shape	-	RECTANGULAR	RECTANGULAR	SQUARE	-	RECTANGULAR
Package form	-	IN-LINE	SMALL OUTLINE	CHIP CARRIER	-	IN-LINE
Peak Reflow Temperature (Celsius)	-	NOT SPECIFIED	260	NOT SPECIFIED	-	NOT SPECIFIED
power supply	-	5 V	5 V	5 V	-	5 V
propagation delay (tpd)	-	56 ns	56 ns	46 ns	-	56 ns
Certification status	-	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified
Maximum seat height	-	5.1 mm	1.75 mm	4.57 mm	-	5.08 mm
Maximum supply voltage (Vsup)	-	5.5 V	5.5 V	5.5 V	-	5.5 V
Minimum supply voltage (Vsup)	-	4.5 V	4.5 V	4.5 V	-	4.5 V
Nominal supply voltage (Vsup)	-	5 V	5 V	5 V	-	5 V
surface mount	-	NO	YES	YES	-	NO
technology	-	CMOS	CMOS	CMOS	-	CMOS
Temperature level	-	MILITARY	MILITARY	INDUSTRIAL	-	MILITARY
Terminal surface	-	Matte Tin (Sn)	Nickel/Palladium/Gold (Ni/Pd/Au)	Matte Tin (Sn)	-	Tin/Lead (Sn/Pb)
Terminal form	-	THROUGH-HOLE	GULL WING	J BEND	-	THROUGH-HOLE
Terminal pitch	-	2.54 mm	1.27 mm	1.27 mm	-	2.54 mm
Terminal location	-	DUAL	DUAL	QUAD	-	DUAL
Maximum time at peak reflow temperature	-	NOT SPECIFIED	30	NOT SPECIFIED	-	NOT SPECIFIED
Trigger type	-	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	-	POSITIVE EDGE
width	-	7.62 mm	3.9 mm	8.9662 mm	-	7.62 mm
Base Number Matches	-	1	1	1	-	1

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