M74HCT165C1R datasheet, PDF - EEWORLD Datasheet

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M74HCT165C1R: Description8 BIT PISO SHIFT REGISTER; Categorylogic logic; File Size262KB，13 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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M74HCT165C1R Overview

8 BIT PISO SHIFT REGISTER

M74HCT165C1R Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	QFN
package instruction	CC-20
Contacts	20
Reach Compliance Code	compli
Other features	CLOCK INHIBIT
Counting direction	RIGHT
series	HCT
JESD-30 code	S-PQCC-J20
JESD-609 code	e3
length	8.9662 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	PARALLEL IN SERIAL OUT
Maximum Frequency@Nom-Su	24000000 Hz
Number of digits	8
Number of functions	1
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC20,.4SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
propagation delay (tpd)	46 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	8.9662 mm
minfmax	24 MHz
Base Number Matches	1

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M54HCT165

M74HCT165

8 BIT PISO SHIFT REGISTER

HIGH SPEED

= 17 ns (TYP.) AT V

= 5 V

LOW POWER DISSIPATION

= 4

µA

(MAX.) AT T

= 25

°C

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

BALANCED PROPAGATION DELAYS

PLH

= t

PHL

SYMMETRICAL OUTPUT IMPEDANCE

I



= 4 mA (MIN.)

COMPATIBLE WITH TTL OUTPUTS

= 2 V (MIN.) V

= 0.8 V (MAX.)

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS165

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

DESCRIPTION

The M54/74HCT165 is a high speed CMOS 8 BIT

PISO SHIFT REGISTER fabricated in silicon gate

MOS technology. It has the same high speed

performance of LSTTL combined with true CMOS

low power consumption. It achives the high speed

operation similar to equivalent LSTTL while

maintaining the CMOS low power dissipation.

This device contains eight clocked master slave RS

flip-flops connected as a shift register, with auxiliary

gating to provide over-riding asynchronous parallel

entry. Parallel data entrens when the shift/load input

is low. The parallel data can change while shift/load

is low, provided that the recommended set-up and

hold times are observed. For clocked operation,

shift/load must be high. The two clock input perform

identically; one can be used as a clock inhibit by

applying a high signal; to permit this operation

clocking is accomplished through a 2 input nor

gates.

To avoid double clocking, however, the inhibit signal

should only go high while the clock is high.

Otherwise the rising inhibit signal will cause the

same response as rising clock edge.This integrated

circuit has input and output characteristics that are

fully compatible with 54/74 LSTTL logic families.

M54/74HCT devices are designed to directly

interface HSCMOS systems with TTL and NMOS

components. They are also plug in replacements for

LSTTL devices giving a reduction of power

consumption. All inputs are equipped with

protection circuits against static discharge and

transient excess voltage.

October 1993

ORDER CODES :

M54HCT165F1R

M74HCT165M1R

M74HCT165B1R

M74HCT165C1R

PIN CONNECTIONS

(top view)

NC =

No Internal

Connection

1/13

M74HCT165C1R Related Products

	M74HCT165C1R	M74HCT165B1R	M74HCT165M1R	M74HCT165	M54HCT165	M54HCT165F1R
Description	8 BIT PISO SHIFT REGISTER	8 BIT PISO SHIFT REGISTER	8 BIT PISO SHIFT REGISTER	8 BIT PISO SHIFT REGISTER	8 BIT PISO SHIFT REGISTER	8 BIT PISO SHIFT REGISTER
Is it Rohs certified?	conform to	conform to	conform to	-	-	incompatible
Parts packaging code	QFN	DIP	SOIC	-	-	DIP
package instruction	CC-20	PLASTIC, DIP-16	SOP, SOP16,.25	-	-	DIP, DIP16,.3
Contacts	20	16	16	-	-	16
Reach Compliance Code	compli	compli	compli	-	-	_compli
Other features	CLOCK INHIBIT	CLOCK INHIBIT	CLOCK INHIBIT	-	-	CLOCK INHIBIT
Counting direction	RIGHT	RIGHT	RIGHT	-	-	RIGHT
series	HCT	HCT	HCT	-	-	HCT
JESD-30 code	S-PQCC-J20	R-PDIP-T16	R-PDSO-G16	-	-	R-GDIP-T16
JESD-609 code	e3	e3	e4	-	-	e0
Load capacitance (CL)	50 pF	50 pF	50 pF	-	-	50 pF
Logic integrated circuit type	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	-	-	PARALLEL IN SERIAL OUT
Number of digits	8	8	8	-	-	8
Number of functions	1	1	1	-	-	1
Number of terminals	20	16	16	-	-	16
Maximum operating temperature	85 °C	125 °C	125 °C	-	-	125 °C
Minimum operating temperature	-40 °C	-55 °C	-55 °C	-	-	-55 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	-	-	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	-	CERAMIC, GLASS-SEALED
encapsulated code	QCCJ	DIP	SOP	-	-	DIP
Encapsulate equivalent code	LDCC20,.4SQ	DIP16,.3	SOP16,.25	-	-	DIP16,.3
Package shape	SQUARE	RECTANGULAR	RECTANGULAR	-	-	RECTANGULAR
Package form	CHIP CARRIER	IN-LINE	SMALL OUTLINE	-	-	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	260	-	-	NOT SPECIFIED
power supply	5 V	5 V	5 V	-	-	5 V
propagation delay (tpd)	46 ns	56 ns	56 ns	-	-	56 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	-	-	Not Qualified
Maximum seat height	4.57 mm	5.1 mm	1.75 mm	-	-	5.08 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	-	-	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	-	-	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	-	-	5 V
surface mount	YES	NO	YES	-	-	NO
technology	CMOS	CMOS	CMOS	-	-	CMOS
Temperature level	INDUSTRIAL	MILITARY	MILITARY	-	-	MILITARY
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)	Nickel/Palladium/Gold (Ni/Pd/Au)	-	-	Tin/Lead (Sn/Pb)
Terminal form	J BEND	THROUGH-HOLE	GULL WING	-	-	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm	1.27 mm	-	-	2.54 mm
Terminal location	QUAD	DUAL	DUAL	-	-	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	30	-	-	NOT SPECIFIED
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	-	-	POSITIVE EDGE
width	8.9662 mm	7.62 mm	3.9 mm	-	-	7.62 mm
Base Number Matches	1	1	1	-	-	1

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