Output transition time (10% to 90% rise/fall time)
@ ƒ
out
< 1 GHz
@ ƒ
out
= 2.5 GHz
@ ƒ
out
= 3.5 GHz
@ ƒ
out
< 1 GHz
|V
out(p-p)
|
4
@ ƒ
out
= 2.5 GHz
@ ƒ
out
= 3.5 GHz
P
Spitback
P
feedthru
H
2
ƒ
out
power level appearing at RF
in
or RF
in
(@ ƒ
in
12 GHz, unused RF
out
or RF
out
unterminated)
ƒ
out
power level appearing at RF
in
or RF
in
(@ ƒ
in
= 12 GHz, both RF
out
and RF
out
terminated)
Power level of ƒ
in
appearing at RF
out
or RF
out
(@ ƒ
in
= 10 GHz, P
in
= 0 dBm, referred to P
in
(ƒ
in
))
Second harmonic distortion output level (@ ƒ
out
= 3.0 GHz, referred to P
out
(ƒ
out
))
4
3.5
0
−15
−15
−15
−10
−4
Min
16
Typ
18
0.2
3.4
> −25
> −20
> −25
> −15
> −10
15
30
−153
1
70
6
5.5
2.0
0.99
0.94
0.63
−40
−47
−23
−25
+10
+10
+10
+10
+4
0.5
Max
Units
GHz
GHz
GHz
dBm
dBm
dBm
dBm
dBm
dB
dB
dBc/Hz
ps
ps
dBm
dBm
dBm
Volts
Volts
Volts
dBm
dBm
dBc
dBc
1. For sine-wave input signal. Prescaler will operate down to D.C. for square-wave input signal. Minimum divide frequency limited by input slew-rate.
2. Prescaler may exhibit this output signal under bias in the absence of an RF input signal. This condition may be eliminated by use of the Input dc offset technique
described on page 4.
3. Fundamental of output square wave’s Fourier Series.
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FPGA/CPLD
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