AD9204BCPZRL7-80 datasheet, PDF

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AD9204BCPZRL7-80: DescriptionAnalog to Digital Converters - ADC IC 10 Bit 80 Msps 1.8V Dual; Categorysemiconductor Analog mixed-signal IC; File Size1MB，36 Pages; ManufacturerADI; Websitehttps://www.analog.com

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Analog to Digital Converters - ADC IC 10 Bit 80 Msps 1.8V Dual

AD9204BCPZRL7-80 Parametric

Parameter Name	Attribute value
Product Category	Analog to Digital Converters - ADC
Manufacturer	ADI
RoHS	Details
Mounting Style	SMD/SMT
Package / Case	LFCSP-64
Resolution	10 bit
Number of Channels	2 Channel
Sampling Rate	80 MS/s
Input Type	Differential/Single-Ended
Interface Type	Parallel, Serial, SPI
Architecture	Pipeline
Reference Type	External, Internal
SNR - Signal to Noise Ratio	61.7 dB
Maximum Operating Temperature	+ 85 C
Minimum Operating Temperature	- 40 C
Packaging	Reel
DNL - Differential Nonlinearity	+/- 0.3 LSB
Gain Error	1.8 %FSR
Height	0.83 mm
INL - Integral Nonlinearity	+/- 0.6 LSB
Input Voltage	2 Vp-p
Length	9 mm
Moisture Sensitive	Yes
Number of ADC Inputs	2 Input
Number of Converters	2 Converter
Operating Supply Voltage	1.8 V
Pd - Power Dissipation	177 mW
Power Consumption	63 mW
Product	Analog to Digital Converters
Sample and Hold	Yes
Factory Pack Quantity	750
Type	S/H ADC
Width	9 mm

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10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,

1.8 V Dual Analog-to-Digital Converter

Data Sheet

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply

SNR

61.3 dBFS at 9.7 MHz input

61.0 dBFS at 200 MHz input

SFDR

75 dBc at 9.7 MHz input

73 dBc at 200 MHz input

Low power

30 mW per channel at 20 MSPS

63 mW per channel at 80 MSPS

Differential input with 700 MHz bandwidth

On-chip voltage reference and sample-and-hold circuit

DNL = ±0.11 LSB

Serial port control options

Scalable analog input: 1 V p-p to 2 V p-p differential

Offset binary, gray code, or twos complement data format

Optional clock duty cycle stabilizer

Integer 1-to-8 input clock divider

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out with programmable clock and data

alignment

AVDD

GND

SDIO SCLK CSB

AD9204

FUNCTIONAL BLOCK DIAGRAM

SPI

CMOS

OUTPUT BUFFER

ORA

D9A

D0A

DCOA

VIN+A

ADC

VIN–A

PROGRAMMING DATA

VREF

SENSE

VCM

RBIAS

VIN–B

ADC

VIN+B

REF

SELECT

MUX OPTION

AD9204

DRVDD

CMOS

OUTPUT BUFFER

ORB

D9B

D0B

DCOB

DIVIDE

1 TO 8

DUTY CYCLE

STABILIZER

MODE

CONTROLS

08122-001

CLK+ CLK–

SYNC

DCS

PDWN DFS OEB

Figure 1.

PRODUCT HIGHLIGHTS

The AD9204 operates from a single 1.8 V analog power

supply and features a separate digital output driver supply

to accommodate 1.8 V to 3.3 V logic families.

The patented sample-and-hold circuit maintains excellent

performance for input frequencies up to 200 MHz and is

designed for low cost, low power, and ease of use.

A standard serial port interface supports various product

features and functions, such as data output formatting,

internal clock divider, power-down, DCO/DATA timing

and offset adjustments, and voltage reference modes.

The AD9204 is packaged in a 64-lead RoHS compliant

LFCSP that is pin compatible with the AD9268 16-bit

ADC, the

AD9251

and

AD9258

14-bit ADCs, and the

AD9231

12-bit ADC, enabling a simple migration path

between 10-bit and 16-bit converters sampling from

20 MSPS to 125 MSPS.

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

Battery-powered instruments

Handheld scope meters

Ultrasound

Radar/LIDAR

PET/SPECT imaging

Rev. A

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

AD9204

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 7

Timing Specifications .................................................................. 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

AD9204-80 .................................................................................. 12

AD9204-65 .................................................................................. 14

AD9204-40 .................................................................................. 15

AD9204-20 .................................................................................. 16

Equivalent Circuits ......................................................................... 17

Theory of Operation ...................................................................... 19

ADC Architecture ...................................................................... 19

Analog Input Considerations.................................................... 19

Data Sheet

Voltage Reference ....................................................................... 22

Clock Input Considerations ...................................................... 23

Power Dissipation and Standby Mode .................................... 25

Digital Outputs ........................................................................... 26

Timing ......................................................................................... 26

Built-In Self-Test (BIST) and Output Test .................................. 27

Built-In Self-Test (BIST) ............................................................ 27

Output Test Modes ..................................................................... 27

Channel/Chip Synchronization .................................................... 28

Serial Port Interface (SPI) .............................................................. 29

Configuration Using the SPI ..................................................... 29

Hardware Interface..................................................................... 30

Configuration Without the SPI ................................................ 30

SPI Accessible Features .............................................................. 30

Memory Map .................................................................................. 31

Reading the Memory Map Register Table............................... 31

Open Locations .......................................................................... 31

Default Values ............................................................................. 31

Memory Map Register Table ..................................................... 32

Memory Map Register Descriptions ........................................ 34

Applications Information .............................................................. 35

Design Guidelines ...................................................................... 35

Outline Dimensions ....................................................................... 36

Ordering Guide .......................................................................... 36

REVISION HISTORY

9/2016—Rev. 0 to Rev. A

Changes to Figure 3 .......................................................................... 7

Changes to Clock Input Options Section .................................... 24

7/2009—Revision 0: Initial Version

Rev. A | Page 2 of 36

AD9204BCPZRL7-80 Related Products

	AD9204BCPZRL7-80	AD9204BCPZ-20	AD9204-80EBZ	AD9204BCPZ-80	AD9204-40EBZ	AD9204-65EBZ	AD9204-20EBZ	AD9204BCPZ-65	AD9204BCPZ-40
Description	Analog to Digital Converters - ADC IC 10 Bit 80 Msps 1.8V Dual	RF Detector 1MHz-4GHz 80 dB	BOARD EVALUATION 80MSPS AD9204	IC ADC 10BIT 80MSPS DL 64LFCSP	EVAL BOARD FOR AD9204	EVAL BOARD FOR AD9204	EVAL BOARD FOR AD9204	IC ADC 10BIT 65MSPS DL 64LFCSP	IC ADC 10BIT 40MSPS DL 64LFCSP
Architecture	Pipeline	Pipeline	-	pipeline	-	-	-	pipeline	pipeline
Number of A/D converters	-	-	2	2	2	2	2	2	2
Number of digits	-	-	10	10	10	10	10	10	10
Sample rate (per second)	-	-	80M	80M	40M	65M	20M	65M	40M
Data interface	-	-	SPI	in parallel	SPI	SPI	SPI	in parallel	in parallel

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