10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
Data Sheet
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
61.3 dBFS at 9.7 MHz input
61.0 dBFS at 200 MHz input
SFDR
75 dBc at 9.7 MHz input
73 dBc at 200 MHz input
Low power
30 mW per channel at 20 MSPS
63 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
DNL = ±0.11 LSB
Serial port control options
Scalable analog input: 1 V p-p to 2 V p-p differential
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
AVDD
GND
SDIO SCLK CSB
AD9204
FUNCTIONAL BLOCK DIAGRAM
SPI
CMOS
OUTPUT BUFFER
ORA
D9A
D0A
DCOA
VIN+A
ADC
VIN–A
PROGRAMMING DATA
VREF
SENSE
VCM
RBIAS
VIN–B
ADC
VIN+B
REF
SELECT
MUX OPTION
AD9204
DRVDD
CMOS
OUTPUT BUFFER
ORB
D9B
D0B
DCOB
DIVIDE
1 TO 8
DUTY CYCLE
STABILIZER
MODE
CONTROLS
08122-001
CLK+ CLK–
SYNC
DCS
PDWN DFS OEB
Figure 1.
PRODUCT HIGHLIGHTS
1.
The AD9204 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO/DATA timing
and offset adjustments, and voltage reference modes.
The AD9204 is packaged in a 64-lead RoHS compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the
AD9251
and
AD9258
14-bit ADCs, and the
AD9231
12-bit ADC, enabling a simple migration path
between 10-bit and 16-bit converters sampling from
20 MSPS to 125 MSPS.
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Ultrasound
Radar/LIDAR
PET/SPECT imaging
2.
3.
4.
Rev. A
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Trademarks and registered trademarks are the property of their respective owners.
AD9204
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 12
AD9204-80 .................................................................................. 12
AD9204-65 .................................................................................. 14
AD9204-40 .................................................................................. 15
AD9204-20 .................................................................................. 16
Equivalent Circuits ......................................................................... 17
Theory of Operation ...................................................................... 19
ADC Architecture ...................................................................... 19
Analog Input Considerations.................................................... 19
Data Sheet
Voltage Reference ....................................................................... 22
Clock Input Considerations ...................................................... 23
Power Dissipation and Standby Mode .................................... 25
Digital Outputs ........................................................................... 26
Timing ......................................................................................... 26
Built-In Self-Test (BIST) and Output Test .................................. 27
Built-In Self-Test (BIST) ............................................................ 27
Output Test Modes ..................................................................... 27
Channel/Chip Synchronization .................................................... 28
Serial Port Interface (SPI) .............................................................. 29
Configuration Using the SPI ..................................................... 29
Hardware Interface..................................................................... 30
Configuration Without the SPI ................................................ 30
SPI Accessible Features .............................................................. 30
Memory Map .................................................................................. 31
Reading the Memory Map Register Table............................... 31
Open Locations .......................................................................... 31
Default Values ............................................................................. 31
Memory Map Register Table ..................................................... 32
Memory Map Register Descriptions ........................................ 34
Applications Information .............................................................. 35
Design Guidelines ...................................................................... 35
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
REVISION HISTORY
9/2016—Rev. 0 to Rev. A
Changes to Figure 3 .......................................................................... 7
Changes to Clock Input Options Section .................................... 24
7/2009—Revision 0: Initial Version
Rev. A | Page 2 of 36
Data Sheet
GENERAL DESCRIPTION
The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit,
20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter
(ADC). It features a high performance sample-and-hold circuit
and on-chip voltage reference.
The product uses multistage differential pipeline architecture
with output error correction logic to provide 10-bit accuracy at
80 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).
AD9204
A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance.
The digital output data is presented in offset binary, gray code, or
twos complement format. A data output clock (DCO) is provided
for each ADC channel to ensure proper latch timing with receiving
logic. Both 1.8 V and 3.3 V CMOS levels are supported and output
data can be multiplexed onto a single output bus.
The AD9204 is available in a 64-lead RoHS compliant LFCSP
and is specified over the industrial temperature range (−40°C
to +85°C).
Rev. A | Page 3 of 36
AD9204
SPECIFICATIONS
DC SPECIFICATIONS
Data Sheet
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
2
MATCHING CHARACTERISTICS
Offset Error
Gain Error
1
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation Error at 1.0 mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance
3
Input Common-Mode Voltage
Input Common-Mode Range
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD
2
IDRVDD
2
(1.8 V)
IDRVDD
2
(3.3 V)
POWER CONSUMPTION
DC Input
Sine Wave Input (DRVDD = 1.8 V)
Sine Wave Input
2
(DRVDD = 3.3 V)
2
Temp
Full
Full
Full
Full
Full
25°C
Full
25°C
25°C
25°C
Full
Full
Full
25°C
Full
Full
Full
Full
Full
AD9204-20/AD9204-40
Min
Typ
Max
10
Guaranteed
±0.1
±0.70
+1.8
±0.30
±0.075
±0.60
±0.15
±0.0
±0.3
±2
0.981
0.993
2
0.06
2
6
0.9
0.5
7.5
1.3
1.005
±0.75
AD9204-65
Min
Typ
Max
10
Guaranteed
±0.1
±0.50
+1.8
±0.30
±0.15
±0.60
±0.25
±0.0
±0.3
±2
0.981
0.993
2
0.08
2
6
0.9
0.5
7.5
1.3
1.005
±0.75
AD9204-80
Min
Typ
Max
10
Guaranteed
±0.1
±0.70
+1.8
±0.30
±0.11
±0.60
±0.25
±0.0
±0.3
±2
0.981
0.993
2
0.08
2
6
0.9
0.5
7.5
1.3
1.005
±0.75
Unit
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
% FSR
% FSR
ppm/°C
V
mV
LSB rms
V p-p
pF
V
V
kΩ
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
1.8
1.9
3.6
35.8/49.6
1.7
1.7
1.8
1.9
3.6
64.8
1.7
1.7
1.8
1.9
3.6
75.2
V
V
mA
mA
mA
mW
mW
mW
mW
mW
33.5/46.4
2.6/4.4
5.0/8.3
59.5/82.1
64.9/91.4
76.7/111
37/37
2.2
61.1
6.5
12.4
108
121.7
150.8
37
2.2
70.3
8.0
15.3
125
141
177
37
2.2
69.5/97.7
128.5
150
Standby Power
4
Power-Down Power
1
2
Measured with a 1.0 V external reference.
Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4
Standby power is measured with a dc input, the CLK active.
Rev. A | Page 4 of 36
Data Sheet
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 2.
Parameter
1
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
f
IN
= 200 MHz
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
f
IN
= 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
f
IN
= 200 MHz
WORST SECOND OR THIRD HARMONIC
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
f
IN
= 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
f
IN
= 200 MHz
WORST OTHER (HARMONIC OR SPUR)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
f
IN
= 200 MHz
TWO-TONE SFDR
f
IN
= 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS)
CROSSTALK
2
ANALOG INPUT BANDWIDTH
1
2
AD9204
Temp
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
Full
25°C
AD9204-20/AD9204-40
Min
Typ
Max
61.7
61.6
61.0
61.6
AD9204-65
Min Typ
Max
61.5
61.4
60.5
61.4
AD9204-80
Min Typ
Max
61.3
61.3
61.3
60.4
61.0
61.1
61.1
61.1
59.5
60
9.8
9.8
9.8
9.6
−78
−78
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
61.0
61.5
61.5
60.1
61.5
59.7
61.2
60
9.9
9.9
9.9
9.8
9.8
9.8
9.6
−78
−78
−65
−82
−78
−73
78
78
65
78
64
75
64
73
−82
−82
−71
−82
−80
−80
78
−100
700
−80
−80
−70
75
75
−64
61.2
61.2
−81
−81
−78
−64
−73
75
75
75
73
−80
−80
−80
−70
−80
78
−100
700
−100
700
See the
AN-835 Application Note,
Understanding High Speed ADC Testing and Evaluation,
for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
Rev. A | Page 5 of 36
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