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71T75602S166PFG

Description
USB Connectors 5P SS R/A RECEP SURF MNT MICRO USB
Categorystorage   
File Size252KB,27 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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71T75602S166PFG Overview

USB Connectors 5P SS R/A RECEP SURF MNT MICRO USB

71T75602S166PFG Parametric

Parameter NameAttribute value
Product CategorySRAM
ManufacturerIDT (Integrated Device Technology, Inc.)
RoHSDetails
Memory Size18 Mbit
Organization512 k x 36
Access Time3.5 ns
Maximum Clock Frequency166 MHz
Interface TypeParallel
Supply Voltage - Max2.625 V
Supply Voltage - Min2.375 V
Supply Current - Max245 mA
Minimum Operating Temperature0 C
Maximum Operating Temperature+ 70 C
Mounting StyleSMD/SMT
Package / CaseTQFP-100
PackagingTray
Height1.4 mm
Length20 mm
Memory TypeSDR
Moisture SensitiveYes
Operating Temperature Range0 C to + 70 C
Factory Pack Quantity72
TypeSynchronous
Width14 mm
Unit Weight0.023175 oz
512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
IDT71T75602
IDT71T75802
Features
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V I/O Supply (V
DDQ
)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Green parts available, see Ordering Information
Functional Block Diagram - 512K x 36
LBO
512Kx36 BIT
MEMORY ARRAY
Address
Address A [0:18]
CE1
,
CE2
,
CE2
R
/
W
CEN
ADV/LD
BW
x
D
Q
D
Q
Control
DI
DO
D
Input Register
Q
Clk
Control Logic
Mux
Sel
Clock
D
Output Register
Q
OE
Gate
Clk
TMS
TDI
TCK
TRST
(optional)
JTAG
TDO
Data I/O [0:31],
I/O P[1:4]
5313 drw 01
OCTOBER 2017
1
©2017 Integrated Device Technology, Inc.
DSC-5313/11
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