Si3232
D
U A L
P
R O G R A M M A BL E
C M O S S L I C
W I T H
L
I N E
M
O N I T O R I N G
Features
Ideal for customer premise applications
Low standby power consumption:
<65 mW per channel
Internal balanced ringing to 65 V
rms
Applications
Cable telephony
Wireless local loop
Description
The Si3232 is a low-voltage CMOS SLIC that offers a low-cost, fully software-
programmable, dual-channel, analog telephone interface for customer premise
(CPE) applications. Internal ringing generation eliminates centralized ringers and
ringing relays, and on-chip subscriber loop testing allows remote line card and
loop diagnostics with no external test equipment or relays. The Si3232 performs
all programmable SLIC functions in compliance with all relevant LSSGR, ITU, and
ETSI specifications; all high-voltage functions are performed by the Si3200
linefeed interface IC. The Si3232 operates from a single 3.3 V supply and
interfaces to a standard SPI bus digital interface for control. The Si3200 operates
from a 3.3 V supply as well as high-voltage battery supplies up to 100 V. The
Si3232 is available in a 64-pin thin quad flat package (TQFP), and the Si3200 is
available in a thermally-enhanced 16-pin small-outline (SOIC) package.
Functional Block Diagram
INT RESET
CS
SCLK
SDI
SDO
VRXPa
VRXNa
VTXPa
VTXNa
VTXPb
VTXNb
VRXPb
VRXNb
VCM
PCLK
Ring Source
Linefeed
& Monitor
SPI
Control
Interface
Ring Source
Linefeed
& Monitor
FSYNC
Preliminary Rev. 0.96 2/05
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Software programmable parameters:
Ringing frequency, amplitude,
cadence, and waveshape
Two-wire ac impedance
DC loop feed (18–45 mA)
Loop closure and ring trip thresholds
Ground key detect threshold
Automatic switching of up to three
battery supplies
On-hook transmission
Loop or ground start operation with
smooth/abrupt polarity reversal
SPI bus digital interface with
programmable interrupts
3.3 V operation
GR-909 loop diagnostics and
loopback testing
12 kHz/16 kHz pulse metering
Lead-free/RoHS compatible
packages available
Ordering Information
See page 122.
U.S. Patent #6,567,521
U.S. Patent #6,812,744
Other patents pending
Voice over IP/voice over DSL
ISDN terminal adapters
Si3232
Si3200
Linefeed
Interface
TIP
RING
Si3200
Linefeed
Interface
TIP
RING
PLL
Copyright © 2005 by Silicon Laboratories
Si3232
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
2
Si3232
Preliminary Rev. 0.96
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Si3232
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1. Linefeed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2. Power Supply Transients on the Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4. Linefeed Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.5. Automatic Dual Battery Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.7. Internal Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.8. Ring Trip Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.9. Ring Trip Timeout Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.10. Ring Trip Debounce Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.11. Loop Closure Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.12. Relay Driver Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.13. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.14. Audio Path Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.15. System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.16. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.17. Si3232 RAM and Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.18. System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5. 8-Bit Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6. 8-Bit Control Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7. 16-Bit RAM Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
8. 16-Bit Control Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9. Pin Descriptions: Si3232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10. Pin Descriptions: Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
11. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
12.1. Part Designators (Partial List) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13. Package Outline: 64-Pin eTQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
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Preliminary Rev. 0.96
3
Si3232
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information
1
Parameter
Supply Voltage, Si3200 and Si3232
High Battery Supply Voltage
2
Low Battery Supply Voltage, Si3200
2
TIP or RING Voltage, Si3200
Symbol
V
DD
, V
DD1
–V
DD4
V
BATH
Test Condition
Continuous
10 ms
Continuous
Continuous
Pulse < 10
s
Pulse < 4
s
Value
–0.5 to 6.0
0.4 to –104
0.4 to –109
V
BATH
–104
V
BATH
–15
V
BATH
–35
±100
±20
Unit
V
V
V
V
V
V
mA
mA
mA
V
°C
°C
°C/W
°C/W
W
W
V
BAT
, V
BATL
V
TIP
, V
RING
TIP, RING Current, Si3200
STIPAC, STIPDC, SRINGAC, SRI-
NGDC Current, Si3232
Input Current, Digital Input Pins
Digital Input Voltage
Operating Temperature Range
Storage Temperature Range
Si3232 Thermal Resistance, Typical
3
(TQFP-64 ePad)
Si3200 Thermal Resistance, Typical
3
(SOIC-16 ePad)
Continuous Power Dissipation,
Si3200
4
Continuous Power Dissipation,
Si3232
Notes:
1.
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2.
The dv/dt of the voltage applied to the V
BAT
, V
BATH
, and V
BATL
pins must be limited to 10 V/s.
3.
The thermal resistance of an exposed pad package is assured when the recommended PCB layout guidelines are
followed correctly. The specified performance requires that the exposed pad be soldered to an exposed copper surface
of equal size and that multiple vias are added to enable heat transfer between the top-side copper surface and a large
internal copper ground plane. Refer to “AN55: Dual ProSLIC™ User Guide” or to the Si3232 evaluation board data
sheet for specific layout examples.
4.
On-chip thermal limiting circuitry will shut down the circuit at a junction temperature of approximately 150 °C. For
optimal reliability, operation above 140 °C junction temperature should be avoided.
4
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I
TIP
, I
RING
I
IN
Continuous
±10
V
IND
T
A
–40 to 100
–40 to 150
25
55
1
T
STG
JA
JA
P
D
P
D
T
A
= 85 °C, SOIC-16
T
A
= 85 °C, TQFP-64
1.6
Preliminary Rev. 0.96
–0.3 to (
V
DD
+ 0.3)
Si3232
Table 2. Recommended Operating Conditions
Parameter
Ambient Temperature
Ambient Temperature
Si3232 Supply Voltage
Si3200 Supply Voltage
High Battery Supply Voltage, Si3200
Low Battery Supply Voltage, Si3200
Symbol
T
A
T
A
V
DD1
–V
DD4
V
DD
V
BATH
V
BATL
Test
Condition
K-grade
B-grade
Min*
0
–40
3.13
3.13
–15
–15
Typ
25
25
3.3
3.3
—
—
Max*
70
85
3.47
3.47
–99
V
BATH
Unit
o
C
o
C
V
V
V
V
*Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25
o
C unless otherwise stated.
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Preliminary Rev. 0.96
5
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