Obsolete Device
Please use SST25VF040B
SST25PF040B
4 Mbit 2.3-3.6V SPI Serial Flash
Features
• Single Voltage Read and Write Operations
- 2.3–3.6V
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
- 80 MHz (2.7-3.6V operation)
- 50 MHz (2.3-2.7V operation)
• Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read Current: 10 mA (typical)
- Standby Current: 5
μA
(typical)
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 32 KByte overlay blocks
- Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
- Chip-Erase Time: 35 ms (typical)
- Sector-/Block-Erase Time: 18 ms (typical)
- Byte-Program Time: 7
μs
(typical)
• Auto Address Increment (AAI) Programming
- Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
- Software polling the BUSY bit in Status Register
- Busy Status readout on SO pin in AAI Mode
• Hold Pin (HOLD#)
- Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
- Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
- Write protection through Block-Protection bits in
status register
• Temperature Range
- Commercial: 0°C to +70°C
• Packages Available
- 8-lead SOIC (150 mils)
- 8-lead SOIC (200 mils)
- 8-contact WSON (6mm x 5mm)
• All devices are RoHS compliant
Product Description
The 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ulti-
mately lowers total system costs. The SST25PF040B
devices are enhanced with improved operating fre-
quency and lower power consumption. SST25PF040B
SPI serial flash memories are manufactured with pro-
prietary, high-performance CMOS SuperFlash technol-
ogy. The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches.
The SST25PF040B devices significantly improve per-
formance and reliability, while lowering power con-
sumption. The devices write (Program or Erase) with a
single power supply of 2.3-3.6V for SST25PF040B.
The total energy consumed is a function of the applied
voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time,
the total energy consumed during any Erase or Pro-
gram operation is less than alternative flash memory
technologies.
The SST25PF040B device is offered in an 8-lead SOIC
(150 mils), 8-lead SOIC (200 mils), and 8-contact
WSON (6mm x 5mm) packages. See
Figure 2-1
for pin
assignments.
2014 Microchip Technology Inc.
DS20005134B-page 1
SST25PF040B
1.0
FUNCTIONAL BLOCK DIAGRAM
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
CE#
SCK
SI
SO
WP#
HOLD#
25134 B1.0
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
DS20005134B-page 2
2014 Microchip Technology Inc.
SST25PF040B
2.0
PIN DESCRIPTION
CE#
SO
WP#
VSS
1
2
8
7
VDD
HOLD#
SCK
SI
CE#
SO
WP#
VSS
1
8
VDD
HOLD#
SCK
SI
2
7
Top View
3
4
6
5
3
Top View
6
4
5
25134 08-soic S2A P1.0
25134 08-wson A P2.0
8-Lead SOIC
FIGURE 2-1:
TABLE 2-1:
Symbol
SCK
8-Contact WSON
PIN ASSIGNMENTS
PIN DESCRIPTION
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
Pin Name
Serial Clock
SI
SO
Serial Data Input
Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#
pin. See
“Hardware End-of-Write Detection” on page 10
for details.
Chip Enable
Write Protect
Hold
Power Supply
Ground
The device is enabled by a high to low transition on CE#. CE# must remain low for
the duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting
the device.
To provide power supply voltage: 2.3-3.6V for SST25PF040B
CE#
WP#
HOLD#
V
DD
V
SS
2014 Microchip Technology Inc.
DS20005134B-page 3
SST25PF040B
3.0
MEMORY ORGANIZATION
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
The SST25PF040B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in
Figure 4-1,
is the
state of the SCK signal when the bus master is in
Standby mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sam-
pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
The SST25PF040B SuperFlash memory array is orga-
nized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable
blocks.
4.0
DEVICE OPERATION
The SST25PF040B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is
used to select the device, and data is accessed through
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
25134 SPIprot.0
HIGH IMPEDANCE
FIGURE 4-1:
SPI PROTOCOL
4.1
Hold Operation
low state, then the device exits in Hold mode when the
SCK next reaches the active low state. See
Figure 4-2
for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be V
IL
or V
IH.
If CE# is driven active high during a Hold condition, it
returns the device to Standby mode. As long as HOLD#
signal is low, the memory remains in the Hold condition.
To resume communication with the device, HOLD#
must be driven active high, and CE# must be driven
active low. See
Figure 5-3
for Hold timing.
The HOLD# pin is used to pause a serial sequence
underway with the SPI flash memory without resetting
the clocking sequence. To activate the HOLD# mode,
CE# must be in active low state. The HOLD# mode
begins when the SCK active low state coincides with
the falling edge of the HOLD# signal. The HOLD mode
ends when the HOLD# signal’s rising edge coincides
with the SCK active low state.
If the falling edge of the HOLD# signal does not coin-
cide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the
active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active
SCK
HOLD#
Active
Hold
Active
Hold
Active
25134 HoldCond.0
FIGURE 4-2:
HOLD CONDITION WAVEFORM
DS20005134B-page 4
2014 Microchip Technology Inc.
SST25PF040B
4.2
Write Protection
4.2.1
WRITE PROTECT PIN (WP#)
SST25PF040B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protec-
tion bits (BP3, BP2, BP1, BP0, and BPL) in the status
register provide Write protection to the memory array
and the status register. See
Table 4-3
for the Block-
Protection description.
The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-
Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see
Table 4-1).
When WP# is
high, the lock-down function of the BPL bit is disabled.
TABLE 4-1:
WP#
L
L
H
CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION
BPL
1
0
X
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
4.3
Status Register
During an internal Erase or Program operation, the sta-
tus register may be read only to determine the comple-
tion of an operation in progress.
Table 4-2
describes
the function of each bit in the software status register.
The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.
TABLE 4-2:
Bit
0
1
2
3
4
5
6
Name
BUSY
WEL
BP0
BP1
BP2
BP3
AAI
SOFTWARE STATUS REGISTER
Function
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
Indicate current level of block write protection (See
Table 4-3)
Indicate current level of block write protection (See
Table 4-3)
Indicate current level of block write protection (See
Table 4-3)
Indicate current level of block write protection (See
Table 4-3)
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
1 = BP3, BP2, BP1, BP0 are read-only bits
0 = BP3, BP2, BP1, BP0 are read/writable
Default at
Power-up
0
0
1
1
1
0
0
Read/Write
R
R
R/W
R/W
R/W
R/W
R
7
BPL
0
R/W
4.3.1
BUSY
The Busy bit determines whether there is an internal
Erase or Program operation in progress. A “1” for the
Busy bit indicates the device is busy with an operation
in progress. A “0” indicates the device is ready for the
next valid operation.
any memory Write (Program/Erase) commands. The
Write-Enable-Latch bit is automatically reset under the
following conditions:
•
•
•
•
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Write-Status-Register instruction completion
4.3.2
WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch bit indicates the status of the
internal memory Write Enable Latch. If the Write-
Enable-Latch bit is set to “1”, it indicates the device is
Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept
•
•
•
•
2014 Microchip Technology Inc.
DS20005134B-page 5
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