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K596-TO-92S

Description
Si N-CHANNEL JUNCTION FET
File Size585KB,3 Pages
ManufacturerJCET
Websitehttp://www.cj-elec.com/

Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); ​​QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

 

 

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K596-TO-92S Overview

Si N-CHANNEL JUNCTION FET

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JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD
TO-92S Plastic-Encapsulate Transistors
TO-92S 
 
1.SOURCE
K596
Si N-CHANNEL JUNCTION FET
FEATURES
Power dissipation
P
CM
: 0.1W(Tamb=25℃)
Gate Current
I
G
: 10mA
Drain current
I
D
: 1mA
Drain-Source voltage
BV
GDO
: -20
V
Operating and storage junction temperature range
T
J
,T
stg
: -55℃ to +150℃
ELECTRICAL CHARACTERISTICS(Tamb=25℃
Parameter
Gate-Drain breakdown Voltage
Gate-Source cut-off Voltage
Drain Current
Forward Transfer Admittance
Input Capacitance
Symbol
BV
GDO
V
GS(off)
I
DSS
|Y
FS
|
C
iss
2.GATE
3.DRAIN
 
                    
 
             123
unless
Test
otherwise
specified)
MIN
-20
-0.6
100
0.4
1.2
3.5
-1.5
800
TYP
MAX
UNIT
V
V
 μA
  ½S
pF
conditions
I
G
= -100μA
V
DS
= 5V , I
D
=1μA
V
DS
= 5 V , V
GS
=0
V
DS
= 5V , V
GS
=0, f=1KHz
V
DS
=5V, V
GS
=0, f=1MHz
V
DS
= 5 V, V =0
GS
Output Capacitance
C
RSS
0.65
pF
f =
1MHz
I
DSS
Classification
Classification
I
DSS
(µA)
A
100-170
B
150-240
C
210-350
D
320-480
E
440-800
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