AME, Inc.
AT209S
n
General Description
The AT209S is an integrated device that contains a PCI
Arbiter and a Clock Buffer. PCI Arbiter extends system
PCI devices without piecing other circuit to simplify de-
sign complexity and increase systems stability.
PCI Arbiter also provides STOP# input pin with that
extended PCI devices instruct the master to prematurely
end the transaction on the current data phase same as
one in PCI specification.
Clock Buffer is a high performance and low jitter zero
delay buffer that provides synchronization between the
input and output. The synchronization is established via
CLKO feed back to the input of a build-in PLL.
PCICLKI is the clock input of the Clock Buffer. In the
absence of PCICLKI input, will be in the power down mode.
In this mode, the PLL is turned off and the output buffers
are pulled low. Power down mode provides the lowest
power consumption for a standby condition.
PCI Arbiter and Clock Buffer
n
Features
l
PCI Arbiter
Extend PCI Devices from One to Three
l
PCI Clock Frequency
Support PCI Clock range from 25MHz to
66MHz
l
Zero delay buffer
Generate four zero delay clock sources
Support frequency range from 25MHz to
66MHz
l
All AME's Lead Free Products Meet RoHS
Standards
Rev.A.01
1
AME, Inc.
AT209S
n
Pin Description
I/O Type
IN
OUT
PWR
PCI Arbiter and Clock Buffer
Function
Input Pin
Output Pin
Power Pin
Pin No.
26
2
3
4
5
7
8
10
11
12
Pin Name
PCIRST#
PCISTOP#
SYSREQ#
SYSGNT#
PCIREQ1#
PCIGNT1#
PCIREQ2#
PCIGNT2#
PCIREQ3#
PCIGNT3#
I/O Type
IN
IN
OUT
IN
IN
OUT
IN
OUT
IN
OUT
PCI bus reset#
Function
PCI bus stop# (Internal 47K pull-up resistor)
Request signal to chipset
Grant signal from chipset (Internal 47K pull-up resistor)
Request signal from PCI bus (Internal 47K pull-up resistor)
Grant signal to PCI bus
Request signal from PCI bus (Internal 47K pull-up resistor)
Grant signal to PCI bus
Request signal from PCI bus (Internal 47K pull-up resistor)
Grant signal to PCI bus
Table 1. PCI Arbiter FSM Group Signal, Power; Vcc3V (3.3V)
Rev.A.01
3
AME, Inc.
AT209S
n
Pin Description
Pin No.
18
19
20
22
23
27
PCI Arbiter and Clock Buffer
Pin Name
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLKOUT
PCICLKI
I/O Type
OUT
OUT
OUT
OUT
OUT
IN
PCICLK output
PCICLK output
PCICLK output
PCICLK output
Function
PLL feedback and Internal feedback on this pin
PCLCLK input reference frequency
Table 2. Clock Buffer Group Signal ---- Power: Vcc23 (2.5V or 3.3V)
Pin No.
6
9
17
21
24
25
28
Pin Name
VSS
VCC
VSS
VCC
VSS
AVSS
AVCC
I/O Type
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Ground
3.3V Power
Ground
3.3V Power
Ground
Ground for PLL
3.3V Power for PLL
Function
Table 3. Power Signal
4
Rev.A.01
AME, Inc.
AT209S
n
Quick Reference Data
GND = 0V; VCC = 3.3V; 0
o
C < Temp < 85
o
C
PCI Arbiter and Clock Buffer
Symbol
VCC
VSS
AVCC
AVSS
Parameter
Power pin
Ground pin
Power pin for PLL
Ground pin for PLL
Test Conditions
Min
3.15
Typical
3.3
0
Max
3.45
Unit
V
V
3.15
3.3
0
3.45
V
V
Table 4. Power/Ground Pin
Symbol
Vil
Vih
Vol
Voh
Duty1
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Output duty cycle
(0.5*VCC as a reference)
Output rise time
Test Conditions
Min
2
Typical
Max
0.8
Unit
V
V
IoI=30mA; VCC3V=3.3V
Ioh=30mA; VCC3V=3.3V
Input duty cycle=50%
Measure between 0.8v and 2V,
2.4
45
0.4
V
V
55
%
Tr
2
CL=30P
Measure between 0.8v and 2V,
CL=30P
Measure at 0.5*Vin & Vout,
nS
Tf
Output fall time
2
nS
Tpd
PCICLKI
Propagation delay time
Buffer input frequency
CL=30P
25M
250
50M
nS
Hz
Table 5. Clock Buffer Block
Rev.A.01
5
PCB Design
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