2SC4115R datasheet, PDF - EEWORLD Datasheet

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2SC4115R: DescriptionTransistor; CategoryDiscrete semiconductor The transistor; File Size966KB，2 Pages; ManufacturerJCET; Websitehttp://www.cj-elec.com/; Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

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2SC4115R Overview

Transistor

2SC4115R Parametric

Parameter Name	Attribute value
Maker	JCET
package instruction	,
Reach Compliance Code	unknow

2SC4115R Preview

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JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD

SOT-89 Plastic-Encapsulate Transistors

2SC4115

TRANSISTOR (NPN)

SOT-89

1. BASE

FEATURES

Low V

CE(sat)

= 0.2V (Typ.)(I

/ I

= 2A / 0.1A)

Excellent current gain characteristics.

Complements to 2SA1585

2. COLLECTOR

3. EMITTER

MAXIMUM RATINGS (T

=25℃ unless otherwise noted)

Symbol

CBO

CEO

EBO

stg

Parameter

Collector-Base Voltage

Collector-Emitter Voltage

Emitter-Base Voltage

Collector Current -Continuous

Collector Power Dissipation

Junction Temperature

Storage Temperature

Value

500

150

-55-150

Units

℃

ELECTRICAL CHARACTERISTICS (Tamb=25℃ unless otherwise specified)

Parameter

Collector-base breakdown voltage

Collector-emitter breakdown voltage

Emitter-base breakdown voltage

Collector cut-off current

Emitter cut-off current

DC current gain

Collector-emitter saturation voltage*

Transition frequency

*pulse test

Symbol

(BR)CBO

(BR)CEO

(BR)EBO

CBO

EBO

CEsat

Test

conditions

MIN

0.1

120

560

0.5

200

290

MHz

TYP

MAX

UNIT

μA

= 50μA, I

=1mA , I

=50μA, I

=30V, I

= 5V, I

=2V, I

= 0.1A

= 2A, I

=0.1A

=2V, I

=0.5 A

F=100MHz

CLASSIFICATION OF h

Rank

Range

marking

120-270

4115Q

180-390

4115R

270-560

4115S

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