Frequency dividing circuit adjusted by potentiometer (CC4013, CH3130)

As shown in the figure is a frequency dividing circuit adjusted by a potentiometer. This circuit uses a serial D/A converter to convert the input data into a voltage value, then compares it with the reference voltage set by the potentiometer, and then feeds back the comparator output to the reset terminal of the counter to obtain the frequency division pulse. The working mode of this circuit is different from the traditional counter feedback frequency divider, because although the traditional method is suitable for fixed integer frequency division, the frequency division coefficient is not easy to adjust. This circuit is particularly suitable for situations where the frequency division coefficient needs to be changed within a wide range. Pictured. CC4520 is a dual four-bit binary synchronous adding counter. It cooperates with the resistor network to turn the input pulse into a staircase wave and sends it to the non-inverting input end of the comparator CH3130. Starting from the initial state of the counter, which is all zero, after n pulses, the ladder voltage exceeds the reference voltage set by the potentiometer, and the comparator output flips to "1". This high level needs to wait for the next rising edge of the clock terminal CL of the flip-flop to output a positive pulse from its Q terminal and reset the counter, and the reset pulse width is exactly equal to one input cycle. Repeat the same process after reset. Obviously, the greater the reference voltage, the greater the number of steps of the staircase wave, and the greater the number of corresponding input pulses, so the frequency division coefficient is also greater. Since the reference voltage comes from the divided voltage of the power supply, the power supply has an impact on the accuracy. It is best to use a regulated power supply. The theoretical maximum frequency division factor of this circuit is 256, but this can only be achieved when the power supply of the operational amplifier is more than 3V higher than the power supply of the logic circuit. If a group of power supplies are shared, considering the input voltage range of the operational amplifier, the maximum frequency division factor can only reach about 200.