ADO Poller

Since the CS550116 analog-to-digital converter lacks a "start conversion" instruction, it continuously converts and outputs to the output register, which has 1024 master clock cycles. However, the ADC can be configured to output a conversion word when it is polled into the circuit via a standard dual JK flip-flop. The CS5501 converter can operate in its asynchronous communication model (UART) to transmit a 16-bit conversion word when it is polled by an RS-232 serial line (see picture). A null character (all 0s) is transmitted to the circuit and sets flip-flop FE2. The CS5501 can output a single conversion word. This conversion word passes through RS-232 as 2 bytes, a start bit and a stop bit. The baud rate can be selected by selecting the appropriate clock division in the clock ADC (SLCK) of the 74HC4040 counter/separator serial port.