Use CD4011 to make a sound and light dual control delay lamp (1)

The sound and light dual control delay energy-saving lamp circuit made with CD4011 digital circuit is shown in Figure 3-17. The left part of the dotted line in the figure is
the ordinary lighting circuit, and the right part is the sound and light double control delay switch circuit. SCR vs. lighting The main loop of the switch and the control
loop are composed of 2 input terminals and four NAND gates CD 4011.
    NAND gate I forms a linear amplifier to amplify the audio signal input by microphone B. NAND gate II forms a light-controlled switch,
and NAND gates III and IV form a monostable circuit. The logic function of the NAND gate is: "When 0 is seen, 1 comes out, and when all 1's come out, 0". During the day, the indoor light
is strong, and the photoresistor RO shows low resistance when exposed to light, so that pin 13 of the input terminal of NAND gate II is low level "0", and
pin II of the output terminal is high level "l", so pin 9 Also "l". Pins 5 and 6 of the two input terminals of NAND gate IV are
low level "0" because Rl0 is grounded, so the output pin 4 is "1" and pin 8 is also "1". Both input terminals of NAND gate III are "l", the output terminal
IO pin is "0", both terminals of capacitor c5 are low level and cannot be charged, and the transistor VT has base resistor R9 connected to pin
4 of the high voltage half. , so VT is turned on, the gate of vs is grounded by VT and turned off, and the light does not light up. Since pin 13 is a low level "o",
no matter how the level of pin 12 changes, the electronic switch is blocked and the lamp cannot be lit.
    At night, the photoresistor RG shows high resistance when there is no light, and its resistance value is much greater than R8, so pin 3 is a high level "l",
which provides conditions for turning on the light, but the level of pin 1 at the output terminal The level depends on the level of pin 12. When someone walks around,
B picks up the sound signal and is coupled to the NAND gate I through cz for amplification, and then charges C4 through R6 (the charging time constant is extremely small) +
making pin 12 also change to high level "l". According to the AND The logical relationship of "all 1's out of 0" in the NOT gate. Pin II outputs low level "0", and
pin 9 is also "O". From "seeing O out of 1", we can know that the IO pin is "l", that is, pin 10 outputs a high level and charges c5 through Rl0. According
to the principle that the voltage at both ends of the capacitor cannot change suddenly, pins 5 and 6 are "l", so pin 4 of the output terminal is low level "O", VT is cut off, and
the door panel of the thyristor VS obtains the positive direction through VD1 and Rl When the electric current is touched and turned on, the electric lamp H is energized and emits light. After about 30
seconds, c5 is fully charged, pins 5 and 6 return to low level "O", pin 4 outputs high level "l", VT seeks to pass, vs loses
the trigger current, and turns off when the AC crosses zero. off, the light goes out. In steady state, pin 10 is low level "0", and c5 can be discharged through Rl0
to prepare for the delay of turning on the light next time.
    VD2, VD3, R2 and C6 form a resistor step-down half-wave rectification and voltage stabilizing circuit, which outputs about 6V DC power for integrated
circuits.