Quartus_II counter commonly used routines and project templates

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Quartus_II counter commonly used routines and project templates [Copy link]

Folder template prj is the directory for project files rtl is the Verilog synthesizable code img is the directory for design-related images (mainly for the convenience of writing documents later) doc is the directory for design-related documents testbench is the corresponding testbench storage directory The ip folder under the prj folder stores the IP core files generated in Quartus II The counter LED flips every 500ms. The system clock is 50M, and the corresponding period is 20ns 500ms = 500_000_000ns/20 = 25_000_000; The counter is reset every 500ms. The Quartus_II source program is as follows: module counter(Clk50M,Rst_n,led); input Clk50M; //system clock, 50M input Rst_n; //global reset, low level reset output reg led; //led output reg [24:0]cnt; //define counter register//counter counting process always@(posedge Clk50M or negedge Rst_n) if(Rst_n == 1'b0) cnt <= 25'd0; //else if(cnt == 25'd24_999_999) else if(cnt == 25'd24_999) cnt <= 25'd0; else cnt <= cnt + 1'b1; //led output control process always@(posedge Clk50M or negedge Rst_n) if(Rst_n == 1'b0) led <= 1'b1; //else if(cnt == 25'd24_999_999) else if(cnt == 25'd24_999) led <= ~led; else led <= led; endmodule