FPGA Simple Design Method for Efficient Design[1241003385]

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FPGA Simple Design Method for Efficient Design[1241003385] [Copy link]

Simple design method for efficient design

In the previous section, we described Mingdeyang's general design method. In the process of explaining the case, we drew a lot of waveform diagrams. Some readers may ask, do we also need to draw a lot of waveform diagrams before writing code at work?

No! At work, the system we have to design is more complex, and there are many signals in a module. If we have to draw waveform diagrams for each module, this is not the simple design advocated by Mingdeyang. What's more, there are many waveform signals drawn for one day, and it is easy to be confused.

The waveform diagrams we drew in the previous section are mainly to let readers understand the relationship between functions, counters and signals more clearly. If we keep Mingdeyang's rules in mind, our design will be very simple. What we need to do is not waveform design, but functional design. Functional design is to write our design code according to functional requirements. Let's take case 4 in the previous section as an example to explain what functional design is. The functional requirement of case 4 is: when receiving en=1, dout generates a high-level pulse of 2 clock cycles after 1 clock interval, and repeats 3 times. From the question, we can know that we need to count the number of "intervals" and "high levels", but there is no signal to indicate "high intervals". For this reason, we think of adding a signal flag_add to indicate the counting area. Interval time + high level time, get the number of counters 3. We see the sentence of repeating 3 times, which means there is another counter counting the number of repetitions. Naturally, we think that we add 1 every time it is completed, and add 3 times in total. The code is as follows. When designing counter 0, a new signal flag_add is added. Then think further, when to generate action, let flag_add be 1. Of course, from the question, we know that en==1 is the start, and when the number of repetitions is completed, it ends, and no signal is generated. So flag_add code.

Finally, let's design dout. From the question, we know that each time after 1, dout changes to 1, and after 2 clocks, it changes to 0. So what do we use to count this 1 and 2? cnt0. In summary, it means that after cnt0 counts to 1, dout changes to 1, and changes to 0 after counting.

Summary: Start from the text description of the function and design the code according to the functional requirements. When designing, you must understand the cause and effect relationship of the signal, such as why it changes to 0 or why it changes to 1, and find the answer from the functional description. If you practice this way of thinking and designing frequently, you can design exquisite code in a few minutes, and the cause and effect and logical relationships are clear, and there is almost no possibility of error, so you can write code that is what you want.