Implementing a 16-bit carry-lookahead adder using Verilog (Example)

settleinsh

Implementing a 16-bit carry-lookahead adder using Verilog (Example) [Copy link]

module cla16 (a,b,s); //top module contains four 4-bit carry-lookahead adder submodules
input [15:0] a, b;
output [15:0] s;

wire pp4,pp3,pp2,pp1;
wire gg4,gg3,gg2,gg1;
wire [14:0] Cp;

wire [15:0] p,g;


claslice i1 (p[3],p[2],p[1],p[0],g[3],g[2],g[1],g[0],1'b0,Cp[2],Cp[1],Cp[0],pp1,gg1);
claslice i2 (p[7],p[6],p[5],p[4],g[7],g[6],g[5],g[4],Cp[3],Cp[6],Cp[5],Cp[4],pp2,gg2);
claslice i3 (p[11],p[10],p[9],p[8],g[11],g[10],g[9],g[8], Cp[7],Cp[10],Cp[9],Cp[8],pp3,gg3);
claslice i4 (p[15],p[14],p[13],p[12],g[15],g[14],g[13],g[12],Cp[11],Cp[14],Cp[13],Cp[12],pp4,gg4);
claslice i5 (pp4,pp3,pp2,pp1,gg4,gg3,gg2,gg1,1'b0,Cp[11],Cp[7],Cp[3],pp5,gg5);

pg i0(a[15:0],b[15:0],p[15:0],g[15:0]);

assign s[0]=p[0]^1'b0;
assign s[1] =p[1]^Cp[0];
assign s[2]=p[2]^Cp[1];
assign s[3]=p[3]^Cp[2];
assign s[4]=p[4]^Cp[3];
assign s[5]=p[5]^Cp[4];
assign s[6]=p[6]^Cp[5];
assign s[7]=p[7]^Cp[6];
assign module claslice( p[3],p[2
],p[1],p[0],g[3],g[2],g[1],g[ 0 ] ,Co, Cp [2],Cp[1],Cp[0],pp,gg) ; //4-bit carry-lookahead adder module input module pg(a,b,p,g); // Carry generation signal, carry transfer signal generation moduleinput [15 : 0] a, b; output [15: 0 ] p,g; assign p = a^b ; assign g=a&b; endmoduleFor reference





























only, if there is any mistake, please point it out!

EdChen

Good stuff.

ys3663391

Have you ever used it to synthesize the effects of area and timing?

huangzhaojun

XIE ;E

wyfiscc

This is nothing, it's just for fun, it doesn't reflect the actual circuit parameters. Where is the delay?

浅滩之鲛

There is something wrong with the simulation results.