Vivado will report an error when generating a bit file!

刘123

Vivado will report an error when generating a bit file! [Copy link]

I want to use the debug method of vivado to see if the program I wrote is correct. However, when I use vhdl to write the process, the sensitive signal will report an error if there is no clock, as shown in the figure below The code I wrote is like this But if I change the code to the one shown below, this problem will not occur Is it just because there is a clock? Is it not possible without a clock? And the following logic is not what I want, I don’t know what to do? Maybe what I said is not very clear. If there are kind experts who want to help me, you can add my QQ 153041342 or comment to give me guidance. Thank you very much.

刘123

After all the changes, this problem reappeared, so annoying. I went to the official website to check, but there was no satisfactory solution.

郝旭帅

Combinatorial logic should not support self-addition, otherwise it will iterate infinitely...

刘123

Hao Xushuai posted on 2018-9-14 12:00 Combinatorial logic should not support self-addition, otherwise it will iterate infinitely...

How should I change it? Although I have already changed it, I still want to know that since combinatorial logic cannot add, what should I use instead?

郝旭帅

If you want to add it yourself, you usually have to use sequential logic, that is, add a register at the end to make a meaningful feedback.

刘123

Hao Xushuai posted on 2018-9-14 17:32 If you want to add it yourself, you usually have to use sequential logic, that is, add a register at the end. Make a meaningful feedback.

But if you use sequential logic, you can't write the result I want. Maybe I can write it, but I didn't think of it

郝旭帅

Then you have to take a good look at this yourself