Libero SoC v11.8 pin optimization issue

凉凉呀凉凉

Libero SoC v11.8 pin optimization issue [Copy link]

 I am a FPGA newbie. Recently, I was programming with Libero SoC v11.8. I defined an input pin in the top-level file. This pin was removed during synthesizing, which made it impossible to constrain this input pin when allocating pins, and thus made the signal unavailable to the FPGA chip. I tried using syntax such as sync keep=1, but it didn't work. Many built-in IP cores also have this problem, and there are a lot of warnings. Please give me some advice!

电子微创意

It is definitely not used, so it has been optimized.

凉凉呀凉凉

Electronic Micro Creativity published on 2018-9-5 21:56 It must be not used, so it was optimized.

凉凉呀凉凉

Electronic Micro Creativity published on 2018-9-5 21:56 It must be not used, so it was optimized.

Take a look, this is my HDL code, input MEMS_SDO, and then call it later

电子微创意

Paste the complete code

teleagle

Sir, you wrote this wrong.

teleagle

Should be: /*synthesis syn_keep = 1*/

gouyang326

How should this be solved?