OMAP5910 is the first highly integrated general-purpose OMAP processor that targets embedded applications. Its application has gone beyond the wireless field and can realize interconnected computing, embedded computing, remote computing and emerging converged computing. It is not only suitable for the 2.5G/3G handheld terminal and PDA market, but also further extends the inherent advantages of the OMAP platform to new customer, commercial and industrial application fields such as digital media, biometric recognition, location services, enhanced games and remote communications. The
OMAP (Open Multimedia Application Platform) processor series includes application processors and integrated baseband application processors, which can provide high performance, real-time processing capabilities and ultra-low power consumption performance. It is widely used in PDAs, Web notepads, remote communications, medical devices, etc. The OMAP5910
processor is a dual-core application processor composed of TI's most widely used TMS320C55X DSP core and a low-power, enhanced ARM925 microprocessor. The 55x series can provide support for real-time multimedia processing for low-power applications; the ARM925 MPU can meet the processing needs of control and interface. Based on the dual-core structure, OMAP5910 has extremely strong computing power and extremely low power consumption. On the one hand, the product has high performance and power saving. On the other hand, like other OMAP processors, it adopts open and easy-to-develop software facilities and supports a wide range of operating systems, such as LinuX, Windows, WincE, Nucleus, Palm OS, VxWorks, Java, etc. When optimizing its application, you can use API and tools that are familiar and easy to use for users.
The structure of OMAP5910TI925T (ARM9TDMI) coreTI925T (ARM9TDMI) core adopts the architecture of 5-stage pipeline 32-bit RISC processor architecture, ARM9 core, and is equipped with Thumb extension. It can process 32-bit or 16-bit instructions and 8-bit, 16-bit, and 32-bit data. This new high-performance, low-power micro-architecture is compatible with the ARMv4T instruction set and the architecture is enhanced by using the coprocessor CP15. The control registers in the system can access the MMU, cache, and read-write cache controller by reading and writing the coprocessor CP15. This micro-architecture provides instruction and data memory management units, instruction, data and write buffers, performance monitoring, debugging and JTAG units and coprocessor interfaces, MAC coprocessor and core memory bus around the ARM core.
The MMU of TI925T has two 64-entry translation bypass buffers (TLBs) for instruction and data streams, each of which can map memory segments, large pages and small pages. In order to ensure the access of instructions and data in the core cycle, TI925T contains a separate 16KB instruction cache and 8KB data cache. Both instruction and data caches are 2-way interrelated caches, operating in blocks of 16 bytes, and using the least recently used (LRU) algorithm to refresh storage. In addition, TI925T also provides a write buffer for improving core performance, which can buffer data up to 17 words.
TMS320C55x (C55x) core The main features of the C55x core are: 1 64×8-bit cache queue, 2 17×17-bit multipliers, 1 40-bit ALU, 1 16-bit ALU, 1 40-bit barrel shifter and 4 40-bit adders. In addition, there are 12 independent buses, namely: 3 data read buses, 2 data write buses, 5 data address buses, 1 program read bus and 1 program address bus, as well as user-configurable IDLE domains. At the same time, the core is mainly composed of 4 units: instruction buffer unit (I unit), program flow unit (P unit), address data flow unit (A unit) and data operation unit (D unit). System
control function The system control module of OMAP5910 provides a real-time clock (RTC), watchdog (WT), interrupt controller, power management controller, reset controller and two on-chip oscillators.
Clock and power management OMAP5910 provides two oscillators to assist in managing power consumption. When designing the system, the 12MHz oscillation input can be directly turned off in standby mode, leaving only the 32KHz oscillator to maintain system operation.
Power management provides three operating modes: Awake mode, Big sleep mode, and Deep sleep mode. In Awake mode, the entire chip runs at the peak frequency, the 32kHz oscillator and the 12MHz oscillator work normally, and when the clock is requested, the 12MHz clock of the peripheral device can be enabled, and the 48MHz clock is generated by the ULPD DPLL or APLL; when the chip generates an IDLE request, the chip works in Big sleep mode, DPLLs 1 and the internal 12MHz clock are turned off; in Deep sleep mode, only the 32KHz oscillator works normally, and the entire system will be in the lowest power consumption state.
EMIFS interface, EMIFF interface, IMIF interface and memory In the OMAP5910 microprocessor core, two expansion memory interfaces are provided. An expansion memory EMIFS interface can support 128MB of ASRAM, FLASH and ROM. Another extended memory EMIFF interface can be set to operate SDRAM, with an address space of up to 128MB. There is also an internal memory area that is used to connect the internal memory of the OMAP5910 microprocessor, which can be used for common data access, such as the image buffer used for the microprocessor LCD screen display. These memory interfaces are all independent operations, and can access data through the microprocessor core at the same time, and can also use DMA data. The control of data transfer between memories is controlled by the flow controller (TC), which will execute data transfer according to the set priority for various transmission requirements.
Peripheral control module The OMAP5910 microprocessor has a DMA controller with 9 independent channels and 7 receive/transmit ports. The DMA controller can respond to requests from internal and external devices, and complete data transfer between external registers, internal registers and external devices under the condition that the MPU TI925T (ARM9TDMI) is running. The setting of the system DMA depends on the MPU TI925T (ARM9TDMI) core. The
OMAP5910 microprocessor also has an independent DMA channel dedicated to the LCD controller. The LCD controller can support monochrome and color STN and color TFT displays. The maximum display resolution is 1024×1024 pixels. In monochrome mode, it can support 15 levels of grayscale; in STN color mode, it supports up to 3375 colors; in TFT display mode, it supports up to 65536 colors. The LCD controller corresponds the pixel encoding value in the frame buffer to the 12-bit wide 256-entry palette RAM, and determines the number of colors according to the data width. Usually, you can choose the on-chip shared SRAM or use the external SDRAM through the EMIFF interface as the frame buffer. To optimize performance, it is recommended to use the on-chip shared SRAM.
The serial ports supported by the OMAP5910 microprocessor include: USB Function and Host module interface based on Universal Serial Bus 2.0 version and Open Host Control Interface 1.0a version; 3 Universal Asynchronous Receiver/Transmitter (UART), two of which have the performance of automatically adjusting the baud rate, and the baud rate adjustment range is between 1200bit/s and 115.2Kbit/s, while the other URAT is usually used as a general URAT or can be used as an IrDA interface; 3 multi-channel buffered serial ports (McBSP), which can provide up to 128 channels of high-speed, full-duplex communication serial interface, can be directly connected to T1/E1 framers, and support devices compatible with MVIP, ST-BUS, IOM2, AC97, I2S and other protocols; 2 multi-channel serial ports (MCSI), which provide full-duplex communication and control functions for master/slave clocks, and at the same time, provide a convenient communication interface for the C55x core to access external devices such as multimedia digital audio decoding encoders or other analog converters; based on Philips I2C-BUS The 2.1 version of the I2C Master/Slave interface supports multi-master mode, that is, all devices on the I2C bus (including OMAP5910) can act as receivers or transmitters; an MMC/SD card interface that supports MMC/SD or SPI protocols and transmits serial data, and an SPI interface.
The OMAP5910 not only meets the inherent target market of the OMAP platform - the development needs of wireless terminals such as 2.5G/3G mobile phones and PDAs, but can also be further expanded to new application areas such as biometric identification, location services, high-end game consoles and remote communications. The single-chip OMAP5910 processor can also become a system chip equipped with a variety of peripherals.
OMAP is so sad and tearful. It's only been a short time since 5 and 4 came out. Comrades in China, how many of you have played it? And then he said he didn't want to do it anymore. Damn it!
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Published on 2015-2-12 11:51
OMAP is so sad and tearful. It's only been a short time since 5 and 4 came out. Comrades in China, how many of you have played it? And then he said he didn't want to do it anymore. Damn it!
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