【PCB drawing experience】PCB and circuit anti-interference measures

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【PCB drawing experience】PCB and circuit anti-interference measures [Copy link]

The anti-interference design of printed circuit boards is closely related to the specific circuits. Here we will only explain several common measures for PCB anti-interference design. 1. Power line design: According to the current size of the printed circuit board, try to increase the width of the power line and reduce the loop resistance. At the same time, make the direction of the power line and the ground line consistent with the direction of data transmission, which will help enhance the anti-noise ability. 2. Principles of ground line design: (1) Separate digital ground from analog ground. If there are both logic circuits and linear circuits on the circuit board, they should be separated as much as possible. The ground of low-frequency circuits should be connected in parallel at a single point as much as possible. If the actual wiring is difficult, it can be connected in series and then connected in parallel. High-frequency circuits should use multi-point series grounding. The ground line should be short and thin. A large area of grid-shaped ground foil should be used around high-frequency components. (2) The ground line should be as thick as possible. If the ground line is a very thin line, the ground potential will change with the change of current, which will reduce the anti-noise performance. Therefore, the ground line should be thickened so that it can pass three times the allowable current on the printed circuit board. If possible, the ground line should be more than 2~3mm. (3) The grounding wire forms a closed loop. For printed circuit boards consisting only of digital circuits, the grounding circuit is usually arranged in a loop to improve noise resistance. 3. Decoupling capacitor configuration: One of the common practices in PCB design is to configure appropriate decoupling capacitors at various key locations of the printed circuit board. The general configuration principles of decoupling capacitors are: (1) A 10~100uf electrolytic capacitor is connected across the power input terminal. If possible, it is better to connect 100uF or more. (2) In principle, each integrated circuit chip should be arranged with a 0.01pF ceramic capacitor. If the printed circuit board space is insufficient, a 1~10pF tantalum capacitor can be arranged for every 4~8 chips. (3) For devices with weak noise resistance and large power supply changes when turned off, such as RAM and ROM storage devices, a decoupling capacitor should be directly connected between the power line and the ground line of the chip. (4) The capacitor lead should not be too long, especially the high-frequency bypass capacitor should not have a lead. (5) When there are contactors, relays, buttons and other components in the printed circuit board. When operating them, they will generate large spark discharges, and an RC circuit must be used to absorb the discharge current. Generally, R is 1~2K and C is 2.2~47UF. (6) The input impedance of CMOS is very high and is easily inductive, so when using it, the unused end must be grounded or connected to a positive power supply.

梦溪开物

Do decoupling capacitors and bypass capacitors mean the same thing?

梦溪开物

The original poster, the pf in this sentence "In principle, each integrated circuit chip should be equipped with a 0.01pF ceramic capacitor. If the printed circuit board space is insufficient, a 1-10pF tantalum capacitor can be placed every 4-8 chips." should be changed to uf, right?

shakencity

The original poster, please come out and say something about this sentence above: "In principle, each integrated circuit chip should be equipped with a 0.01pF ceramic capacitor. If the printed circuit board space is insufficient, a 1~10pF tantalum capacitor can be placed every 4~8 chips." The "pf" in it should be changed to uf, right?