Implementation mechanism of SLC and MLC

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Implementation mechanism of SLC and MLC [Copy link]

Nand Flash can be divided into SLC and MLC according to the different voltage levels of the internal storage data unit, that is, whether a single memory cell stores 1 bit of data or multiple bits of data: 1. SLC, Single Level Cell: A single storage cell stores only one bit of data, represented as 1 or 0. As introduced above, for the representation of data, the voltage of the charge stored inside a single storage cell is compared with a certain threshold voltage Vth. If it is greater than this Vth value, it represents 1, otherwise, it is less than Vth, which represents 0. For writing 1 to the data of nand Flash, it is to control the External Gate to charge so that the stored charge is enough to exceed the threshold Vth, which represents 1. For writing 0, it is to discharge it and reduce the charge to less than Vth, which represents 0.

As to why Nand Flash cannot change from 0 to 1, my understanding is that, physically, it is possible to change each bit from 0 to 1, but in fact, for the actual physical implementation, for efficiency considerations, if each storage unit can be controlled individually, that is, 0 to 1 means charging each storage unit individually, the required hardware implementation is very complex and expensive. At the same time, the block erase operation cannot achieve the previous flash speed, and many characteristics of Flash are lost.

// That is, the idea of discharge is still easier. 1->0

2. MLC, Multi Level Cell:

Corresponding to SLC, it is a single storage unit that can store multiple bits, such as 2 bits, 4 bits, etc. Its implementation mechanism is relatively simple. It is to control the amount of internal charge and divide it into multiple thresholds. By controlling the amount of charge inside, we can achieve the storage of different data as we need. For example, assuming that the input voltage is Vin = 4V (there is no such voltage in reality, it is just for the convenience of example), then we can design 2 to the power of 2 = 4 thresholds, 1/4 of Vin = 1V, 2/4 of Vin = 2V, 3/4 of Vin = 3V, Vin = 4V, which represent 2-bit data 00, 01, 10, 11 respectively. For writing data, it is charging. By controlling the amount of internal charge, different data are represented accordingly.

For reading, it is through the corresponding internal current (inversely proportional to Vth), and then through a series of decoding circuits to complete the reading and parse the stored data. These specific physical implementations all require sufficiently precise equipment and technology to achieve accurate data writing and reading.

A single storage unit that can store 2 bits of data is called 2 to the power of 2 = 4 Level Cell, not 2 Level Cell;

Similarly, for the newly released single storage unit that can store 4 bits of data, it is called 2 to the power of 4 = 16 Level Cell.

Shenzhen Leilong Development Co., Ltd. has been engaged in the NANDFLASH industry for more than 10 years. Currently, it is the agent of ATO Solution small capacity SLC NAND, SPI NAND, MCP, etc. For more information, please consult QQ: 2852826868; Tel: 13691982107

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