Who has done packaging modeling?

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Who has done packaging modeling? [Copy link]

I want to learn about package modeling. I wonder which expert can provide some information for learning.

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Package design for high-performance ICs
Package design is not just about picking a style for assembly, but more about becoming part of IC and system design. If the package factor is not considered early in the design stage, the high-speed signals in the IC may never be transmitted to other components on the PCB. Developers and designers have approached the international advanced level in IC electrical performance design, but often ignore the process requirements. This article introduces a high-performance IC package design concept to solve the problem of device performance degradation caused by improper use of the package.

Today's ICs are facing tremendous pressure to change the package. The higher the number of I/Os, the more complex the connection path from the chip to the package becomes. In addition, high-speed clocks and fast signal rise times will also produce high-speed transmission line effects and crosstalk or electromagnetic interference in the connection, thereby reducing the overall performance of the IC.

To solve these problems and to make the packaged IC have good performance, package design is becoming a new discipline in its own right. Package designers must understand electrical performance issues and study the interaction between the chip and the package. They must also learn how to use more complex EDA software to make the IC meet physical and electrical performance design rules.

Package design is no longer just about picking a style for assembly. It is more of a part of IC and system design. It should be considered as a special multi-application design discipline and advanced packaging software should be integrated into the chip and system design process. This will enable designers to accelerate product design cycles by using packaging technology when they encounter difficulties with bonding and flip chip substrate technology. VLSI Technology has changed its design process to respond to this new situation. In the past, when we designed a new IC package, we first used AutoCAD to make a design sketch, draw the location of the chip and connection points, and then sent it to another substrate material supplier or packaging supplier. They re-drew the drawings using their own CAD tools and returned the Gerber drawing files or AutoCAD files for confirmation.

This method is not a problem for designs with leaded packages, and it can even be used for relatively simple low-pin count BGA device package designs (if there are only one or two in a year). With the increasing number and complexity of new generation VLSI products, this process is increasingly unable to adapt. In order to provide multiple different package options for each IC, we must complete more package designs in a shorter time, and the increase in pin counts and the need for electrical performance optimization further increase the complexity of the drawings.

Because we outsourced a lot of work, the design process was long, and it became increasingly difficult to communicate design requirements with suppliers in distant locations based on sketches. Sometimes subcontractors did not understand why we wanted a certain layout and would make it worse. For example, they connected in a way that was functionally incorrect. When we found out, we had to review the layout we wanted, make corrections, and then send it to the supplier to start over. And they often misunderstood the modified drawings we drew by hand, which increased the number of corrections and caused delays. Therefore, the time from the initial package sketch to the final drawing was very long.

Because a lot of time was spent on reviewing and modifying the design, the old method not only reduced efficiency but also often did not achieve the best results. When we realized that we needed to strengthen the control of the design process to shorten the design cycle, optimize the performance of the chip and package, and improve the yield, we decided to do the package design ourselves and modify the design process so that we could consider various design factors such as chip, package and circuit board at the same time. The purpose was to optimize the performance by considering the IC and its package as a whole from the beginning instead of just treating the package as a back-end process. Now many other chip and system suppliers are beginning to follow this trend. Designing the substrate ourselves was a strategic decision that revolutionized the entire process of package design.

New Technology Application

Based on our experience in advanced package design, we found that the design tools and design methods we had been using in the past had many limitations. Although the drawings produced by traditional design tools looked good, they did not necessarily follow the electrical and physical design rules, and data could not be extracted from them for modeling and analysis.

To optimize performance, software tools that can perform electrical performance design and analysis for advanced packages were needed. Such tools provide internal database access, predetermine the manufacturing, assembly and electrical characteristics of the process during the design process, and finally generate photographic drawings directly for the substrate subcontractor. P> We were looking for design automation tools that can clearly analyze the substrate interconnect design based on advanced package requirements, and also enable the package to support more bare die features, such as new parameters unique to high-performance chips (including multiple voltage settings for different power planes, high-speed I/O, differential pairs, impedance matching, and fixed impedance). In addition to various application signals, the package must also support a large number of other important signals and I/O buses.

In selecting a new package design tool, we evaluated commercial package design tools from several vendors. We designed a formal "review requirements" document, reviewed about 100 items, and then determined that the features we needed most were as follows:

1. The ability to start designing with or without a netlist: For a single chip design, it is usually more efficient to start without a netlist, so that the focus can be on improving density and electrical performance, and then generate the actual chip-to-pin netlist according to other considerations. On the other hand, there are occasionally some chip packaging that needs to be completed according to a pre-defined netlist.

2. The ability to construct a hierarchical database of "components" unique to BGA designs: such as BGA pins, trapezoidal vias, solder points/reference points, and arrays and routing forms that avoid flip chip pads.

3. An interactive autorouter that can achieve very high routing density: devices can generally be routed at any angle, can "push" wires out of the way when routing, and automatically follow BGA design rules.

4. The ability to automatically generate solder joints: Manually constructing solder joints according to manufacturing process requirements would be a very tedious and patient process.

5. Ability to integrate design and manufacturing rule checking (DRC): Integrated rule checking helps in initial electrical analysis, thermal analysis and process verification during the design process.

6. Ability to integrate first-class analysis software into the design process: First-class analysis software should be added to the design process for detailed analysis and description.

7. Ability to import and export common data formats: To ensure applicability, the tool must support data formats used in other design stages, such as DXF, GDS Ⅱ and Gerber.

We chose a very complex single-chip BGA package designed with existing chip design tools as a test standard, so that the performance of the candidate tools can be compared with our existing technology. After trying products from several industry-leading EDA vendors, we chose Encore software from Xynetix Design System. We like Encore's interface and feel, as well as its built-in "smart features". In fact, it is designed specifically for single-chip and multi-chip packages, providing an open environment that can integrate analysis into the design process. A key factor in the selection criteria for

universal interconnect modeling

is that it must be able to generate package interconnect models for our internal and external users, because they need package models to complete chip and system-level circuit simulations. Therefore, VLSI worked with Xynetix and Ansoft to incorporate Ansoft's 2D and 3D parameter extraction tools into the Encore design environment.

The integration of the two software allows engineers to launch analysis tools from within Encore, which is much more convenient than having to switch back and forth between the design and analysis environments, and the analysis tools are easier to set up and use. Engineers can select nets by group, net category, or individual nets, and all interconnects such as wire bonds and BGA balls are automatically extracted. The Ansoft tool uses Encore's layout data to build a 3D model of the interconnects (Figure 2), and then generates RLC matrices and parasitic parameters that can be used to generate Spice models for system simulation. This integration is currently in the beta stage, and the open architecture ensures that we can easily add other analysis tools as needed.

Streamlined workflow

So far, Encore has proven that it can meet our needs. We completed a pilot 596-ball, four-layer design and are currently working on a second design - a four-layer EPBGA with about 700 balls and 1mm pitch, with multiple different voltage zones. Both designs use the tool's automatic wiring capabilities. We are currently working on a flip chip design with 1,160 balls and 1mm pitch, and we are also using multi-layer assembly techniques to create complex via structures.

We hope to use Encore to streamline the design process so that subcontractors do not have to re-enter our design and do multiple reviews and corrections. We can also optimize the performance of the packaged chip by analyzing the design before sending it to the supplier (see Figure 3).

Note that AutoCAD still has a strong role in our design process. It is a good design tool and has become the de facto industry standard. We use it to import the supplier's existing AutoCAD drawings and generate manufacturing assembly drawings. Encore can read DXF data directly and convert it into "smart" data so that it can be processed within Encore. At the same time, we can complete DRC verification, change the design to optimize performance, and convert the design to the DXF format used by AutoCAD.

Although the new design tool allows us to optimize the performance and process of the package design, it also requires new design thinking and skills from the package designer.

Encore automates most of the work, such as automatically rounding pads and vias during routing, which is necessary for a good and manufacturable design. Automation saves a lot of time and improves results. But for package designers who mainly use AutoCAD for pin structure design and have rich experience in this area, the main advantages of the tool - electrical performance planning and following design rules are new. There is a big gap here, because we not only need to be trained on tools, but also learn overall design and layout techniques with electrical performance planning, but this is a necessary change to get a new generation of ICs. A further change

is that we must strive to make package design an integral part of the entire chip design process. The open architecture of the tool is very helpful for this synthesis, which allows designers to predict how the final package will affect the performance of the entire device and system. The tool provides process links, post-verification, electrical and thermal analysis, and direct access to other tools through "backstage consultants" to monitor during the design process. This backstage tool allows us to check electrical, thermal, manufacturing and system-level design parameters before actual output, helping to optimize the performance of the design by eliminating delays and reducing the number of iterations between design and manufacturing departments.

EDA tools can greatly improve design speed and provide packaging solutions for deep submicron devices. We set an internal goal to convert the entire design process within two weeks to optimize the electrical performance of ICs. We believe that this goal is realistic and it is just adding the latest EDA technology to the existing foundation.

Why use advanced IC packaging?

Advanced ICs require advanced packaging technologies, such as ball grid array (BGA), chip scale packaging (CSP) and flip chip interconnects. The advantages of these packages are:

1. Higher I/O count: With the current increase in IC integration, the number of I/Os is also increasing dramatically, and this number continues to grow. Today, devices with 300 to 500 pins are very common, and will soon reach 1,000 to 2,000 pins. The Semiconductor Industry Association (SIA) predicted in its 1997 US Semiconductor Technology Trends Report that semiconductor devices will develop to 5,000 pins in 2012. BGA packaging has become the preferred packaging form for high I/O pin devices, and its pitch is reduced by 200% compared to pin packaging.

2. Performance enhancement: Advanced packaging technology can improve the overall performance of devices by 40% compared with pinned packages, partly due to the reduction of parasitic induction between the chip and the package interconnection, and such problems will continue to increase with the increase of chip speed and density.

3. Size and strength: Advanced packaging can reduce the volume and weight of the system. This advantage is particularly important for consumer electronics. The use of miniaturized chip packaging can make bulky products small and exquisite. In addition, BGA packaging can also avoid manufacturing problems such as easy breakage of pins inherent in fine-pitch devices.

- Author: bleuame

gaoyanmei

Summary: Customers and partners are eager to learn about Microsoft 's strategy for model-driven development and its support for Visual Studio Team System . When our strategy is explained to them, they often show interest in some of the same topics and raise some of the same concerns. In this article, we describe the strategy for model-driven development and a series of questions and answers that developers often involve. The first five questions involve the main structure of our strategy, and we will answer and explain them in detail. Other common questions are concentrated in the general FAQ section in the last part.