Application of EDA Technology in Intelligent Thyristor Trigger Circuit

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Application of EDA Technology in Intelligent Thyristor Trigger Circuit [Copy link]

Abstract: This paper introduces a programmable control digital phase-shift thyristor trigger circuit, which uses FPGA (field programmable gate array) chip and VHDL hardware description language programming. This circuit has phase sequence adaptive function and good stability, and is suitable for three-phase full-controlled rectification and voltage regulation.

Keywords: electronic equipment automation; thyristor; digital phase-shift trigger; VHDL; phase sequence adaptation

　

　

0 Introduction

The phase-shift trigger is an important component of the thyristor power electronic device. Its performance is directly related to the performance index of the entire power electronic device, so it has always been valued by people. The analog trigger circuit commonly used in the past has many disadvantages, which brings many inconveniences to debugging and use. In recent years, digital phase-shift trigger technology has developed rapidly, and a variety of trigger integrated circuits with single-chip microcomputers, dedicated microprocessors and programmable gate arrays as the core have emerged. This paper uses the EPF10K10 chip of ALTERA Company and VHDL language to design a dual-pulse column three-phase thyristor digital phase-shift trigger circuit with full digital phase-shift technology as the core, phase sequence adaptation and pattern recognition functions for voltage regulation and rectification.

1 Working principle of three-phase thyristor phase-controlled trigger circuit

The main function of the trigger circuit is to realize the phase shift control of the thyristor according to the power synchronization signal and the control signal.

For three-phase fully controlled rectification or voltage regulation circuits, the trigger pulses output sequentially are required to be spaced 60° apart. This design adopts a three-phase synchronous absolute triggering method. According to the rising and falling edges of the single-phase synchronization signal, two synchronization points are formed, and two trigger pulses with a phase difference of 180° are respectively issued. Then, the pulse forming unit composed of this circuit belonging to the three phases outputs 6 pulses, and then the complementary pulse forming and distribution unit forms complementary pulses and outputs 6 pulses in sequence.

2 Implementation of EDA Design

This unit module includes PULSE (pulse formation, modulation and protection) module and PULSE_ASSIGN (complementary pulse formation and pulse distribution) module. The whole circuit is composed of three sets of identical single-phase trigger pulse forming circuits. Each phase forms two positive and negative trigger pulses. The six pulses are output as six double narrow complementary pulses through the complementary pulse forming and distribution module. According to the arrival time of the rising edge or falling edge of the synchronization signal a_input (or b_input, c_input), a nine-bit counter is used for counting. When the count value is equal to the value input at the pulse_input terminal (phase control signal input terminal), the corresponding trigger pulse is output. The external system clock is divided into a modulation pulse to modulate the trigger pulse. When the protection terminal pulse_enable input is '1', the trigger pulse is not output, and when it is '0', it is output normally, thereby realizing the protection function. The basic principle block diagram is shown in Figure 1.

Figure 1 Principle block diagram of pulse forming, distribution, modulation and protection unit

2.1 PULSE module

This module completes the pulse forming, modulation and protection functions. The submodule circuit is shown in Figure 2 and is divided into four parts, namely, part A converts the synchronous control pulse signal Syn_A into positive and negative half-cycle synchronous control levels.

Figure 2 PULSE module circuit

Part B completes the phase shift function. C255 is a 255-base counter, and its clock Clk2 is 25kHz. The counting result is compared with the input phase control signal data through comparators T1 _and T2 _, thereby realizing the phase shift function.

Part C realizes the pulse width forming function through the 25-bit counter C25. The pulse width can also be changed by changing the internal parameters online.

Part D implements the pulse width modulation function.

The VHDL hardware description language program for Part B is given below:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

USE ieee.std_logic_unsigned.all;

ENTITY pulse IS

PORT

( clk2 : in std_logic;

syn_output1 : in std_logic;

syn_output2 : in std_logic;

pulse_data : in std_logic_vector(7downto0);

out1,out2 : outs td_logic

);

END pulse;

ARCHITECTURE a OF pulse IS

signal out1,out2:std_logic;

signal count1,count2:std_logic_vector(7downto0);

BEGIN

pulse_generator1:process(clk2)

begin

IF syn_output1='0' THEN

count1<="11111110";

out1<='0';

elsif(clk2'eventandclk2='1')then

count1<=count1－1;

if(count1>pulse_data)then

out1<='0';

else

out1<='1';

count1<="00000000";

end if;

end if;

END PROCESS pulse_generator1;

pulse_generator2:process(clk2)

begin

IF syn_output2='1' THEN

count2<="11111110";

out2<='0';

elsif(clk2'eventandclk2='1')then

count2<=count2－1;

if(count2>pulse_data)then

out2<='0';

else

out2<='1';

count2<="00000000";

end if;

end if;

END PROCESS pulse_generator2;

end a;

2.2 PULSE_ASSIGN module

This module completes the functions of supplementary pulse formation and pulse distribution. In order to ensure that one thyristor in each of the common cathode group and the common anode group conducts after the rectifier bridge is closed, trigger pulses must be sent to the pair of thyristors that should be turned on in the two groups at the same time. For example, when V _T1 is required to be turned on, in addition to sending a trigger pulse to V _T1 , a trigger pulse must also be sent to V _{T6 at the same time; when V T2} is triggered , a trigger pulse must be sent to V _T1 at the same time, etc.

The compensation pulse formation scheme is as follows:

out1<=in1orin6;

out2<=in6orin3;

out3<=in3orin2;

out4<=in2orin5;

out5<=in5orin4;

out6<=in4orin1;

Among them: in1, in2, in3, in4, in5, in6 correspond to the positive and negative pulses of phase A, phase B, and phase C of the PULSE module respectively. Out1, out2, out3, out4, out5, out6 are output to thyristors 1-6 in the corresponding rectifier circuit.

3 Simulation and Experimental Results

In order to verify the effectiveness and feasibility of the above design, the performance of the trigger was tested by program software simulation, single-phase actual circuit test and three-phase closed-loop system, and good simulation and experimental results were obtained.

3.1 Simulation Results

The above program was simulated using ALTERA's MAXPLUSII software. Figure 3 is the simulation waveform of the 6-way trigger pulse circuit. a_input, b_input and c_input are three-phase synchronous input signals with an interval of 120°; 1, 2, 3, 4, 5, 6 are trigger output signals corresponding to the gates of thyristors 1 to 6, respectively. It can be seen that the result is relatively ideal.

Figure 3 6-channel pulse output simulation waveform

3.2 Single-phase experimental test waveform

According to the above simulation results, the hardware experimental circuit was tested. Figure 4 shows the A-phase synchronization signal and its corresponding trigger pulse waveform of thyristor No. 1 at a typical control angle. In order to make the waveform clearer, the trigger pulse waveform without modulation is shown here.

(a) Waveform when α=0°

(b) Waveform when α=90°

Figure 4 Typical control angle synchronization signal and output pulse waveform

4 Application in three-phase rectification system

The above-mentioned trigger pulse forming circuit and the programmed program are used to form a three-phase thyristor trigger, which is used in a three-phase fully controlled rectifier system. The thyristor model used is PK55F120 produced by Sansha Electric Co., Ltd. of Japan, with a resistive load. As a result, the output voltage is continuously adjusted, and the voltage adjustment range can be adjusted from 0V to the rated output voltage of 510V, corresponding to the trigger control angle α of 0°~120°. The experiment proves that the trigger can operate stably, and its adjustment output is continuous and smooth, with satisfactory results. Figure 5 (a) and (b) respectively show the output waveforms of the three-phase fully controlled rectifier circuit with α=60° and α=0° measured by the Hall voltage sensor.

(a) α = 60°

(b) When α = 0°

Figure 5 Typical output voltage waveform

5 Conclusion

In summary, by using three-phase power synchronization, taking FPGA devices as the core, and using software online programming methods, a three-phase phase sequence adaptive thyristor trigger can be made. Theoretical analysis, simulation and experimental results have proved that the design of the three-phase trigger is simple and feasible. This method enables the function of the entire trigger to be realized with one integrated circuit chip, so it has strong anti-interference ability, and both hardware and software are very economical. There is no doubt that it has broad application prospects in power electronic converters with thyristors as the main power devices.