System Solution for Car-mounted Mobile TV Reception

frozenviolet

System Solution for Car-mounted Mobile TV Reception [Copy link]

The introduction of DVB T (Digital Broadcasting Terrestrial) digital television in Berlin has also had an impact on TV reception in car entertainment systems. Car TV receivers are now not only able to receive analog TV signals (which will continue to exist for several years outside of cities), but also to receive and process DVB T signals. Hirschmann Electronics has developed an FPGA-based "hybrid TV receiver" to meet these emerging requirements. The new hybrid receiver also uses improved diversity algorithms for better analog reception quality.
Analog TV transmitters were originally planned for fixed home users, where a directional antenna on the roof provided a clear picture. Antennas for mobile TV reception, however, are usually placed much lower. Not only do the antennas vary in height, but directional antennas cannot be used in this case because the received signal changes constantly as the car moves along its route. In addition, the received signals overlap each other due to scattering and refraction by buildings or other vehicles. This results in signal losses (Rayleigh amplitude distribution).
The first generation of DVB T networks in Germany (Berlin) was designed for portable reception, not mobile reception. Therefore, a "diversity" system with multiple antennas is required to achieve satisfactory TV reception in the car. For example, with the "scanning diversity" technique, the system automatically switches between the different antennas, selecting the one with the highest reception level. For analog TV, this switching can be done separately for video and sound, because the carriers of video and sound differ by 5 MHz and are subject to interference from different sources.
Hirschmann's receiver has a modified and dedicated process for analog TV with superimposed received signals. The signals are first scanned, then time-synchronized, and then the quality of each individual signal is measured. This test method determines "weighting factors". These weighting factors are multiplied by each received signal. This process results in a signal with a better signal-to-noise ratio than a single best received signal.
The DVB T receiver antenna uses MRC (maximum ratio combining) diversity. In this way, the best carrier signals are combined to form the output signal, ensuring good reception quality for car TV even when the vehicle is running at speeds of more than 100 km/h (60 mph).
Frequency diversity works independently of antenna diversity: during reception, the Hirschmann hybrid TV receiver scans the transmitter without any operation on the user part. If a channel is found that carries the same content but with better reception, the device automatically switches to the new channel. This allows the user to watch programs continuously while traveling without having to tune manually when the car passes through the coverage area of a transmitter. The block diagram
of the receiver architecture
is an example of a Hirschmann hybrid TV receiver with three-way reception. Although the system can increase or decrease the number of possible reception channels, two to four channels are generally recommended. A larger number of reception channels will improve reception quality, but it will also increase or decrease the system hardware and software complexity.
The input signal used by the tuner is the RF signal received from the integrated antenna - the dish antenna is usually connected to a separate tuner through a controlled amplifier. The tuner is a hybrid tuner that can receive any standard analog signal and DVB-T signals. For analog reception, the corresponding demodulator is integrated in the tuner. During analog reception, the analog-to-digital converter scans the analog video and audio signals and sends them to the FPGA device of the hybrid receiver. During
DVB-T reception, the coded orthogonal frequency division multiplexing (COFDM) demodulator will send out the MPEG data stream. Independent COFDM demodulators are connected together to achieve the required MRC diversity and optimize the MPEG data stream. The MPEG decoder extracts the video, audio, and data signals from the MPEG data stream. These signals are then also sent to the FPGA. The MPEG decoder is connected to the external SDRAM memory.
Using FPGAs for Digital Signal Processing
All digital signal processing, including antenna diversity for analog video and sound, baseband sound processing, decoding of teletext and other data content such as video program system (VPS), management and storage of this information in SDRAM memory, and communication with the control host through the serial port, can be completed in the Altera Cyclone EP1C12 FPGA. Cyclone FPGAs not only provide logic and arithmetic functions, but the RAM in them can also be used for functions such as FIFOs.
The designers of the Hirschmann diversity receiver took full advantage of Altera's development tools to create the complex units required to support the system functions. For example, Altera's FIR compiler can automatically generate finite impulse response filters (FIR), and the SOPC Builder tool can generate the controller system. The controller includes the Nios embedded processor, as well as RAM, serial ports, and SDRAM controllers. The configuration data for the FPGA is stored in the EPCS4 serial Flash memory and is loaded into the FPGA when the receiver is turned on.
Graphics data processed by the FPGA is sent to the digital-to-analog converter to display the analog signal on the TV screen. The audio digital signal sent from the FPGA is sent to the MOST receiver and then to the MOST bus. When the user enters control commands through the MMI, these commands are also sent to the transceiver through the MOST bus. The host controller communicates with the configurable part of the receiver and manages the control functions of the entire system.
Low-cost FPGA
The low-cost Cyclone EP1C12 device used in the Hirschmann TV receiver has more than 12,000 logic cells and 234Kbits of embedded memory. All five devices in the family are available in the automotive temperature range (-40°C to +125°C). The embedded memory in these devices consists of multiple 4,608-bit memory blocks, which can quickly access local data memory resources. Each memory block supports multiple configurations, including true dual-port and single-port RAM, ROM and FIFO. Because Cyclone FPGAs provide dedicated interfaces, they can be easily configured to communicate with DDR-SDRAM or FCRAM. This interface has fast and reliable data transfer performance of up to 266Mbps.
The Cyclone device family has eight low-skew global clock networks that are distributed throughout the chip and fed by four dedicated clock pins. For clock management of the entire system, the device's PLLs (each with three output taps) are also capable of frequency synthesis and phase offset.
FPGA Systems with Embedded Processors
Cyclone FPGAs are clearly optimized for processor-based applications, especially those that benefit from embedded soft-core processors such as Altera's Nios processors. A typical Nios controller system consists of a CPU, on-chip RAM and ROM, an external memory controller, and many serial and parallel interfaces. Such a Nios-based system requires approximately 1,500 logic elements (LEs), which occupies 12.5% of the effective logic resources of the Cyclone EP1C12 device.
All Nios modules can be connected to the Avalon bus through a multi-master switch matrix. The Nios processor is a five-stage pipelined 16- or 32-bit RISC processor based on the Harvard architecture with completely separated data and address buses. The Avalon switch matrix fully supports the above buses. The synchronous interface, low resource utilization and optimized performance of the Nios processor make it extremely suitable for implementation in programmable logic. Other features include a large register set of up to 512 registers and up to 64 interrupts with adjustable priorities.
Users of the Nios processor can also add special instructions to the Nios processor design. These instructions are processor commands that are implemented in hardware by the user. For example, a multiplication function that is estimated to take 80 clock cycles in software can be executed in only two cycles with special instructions. This allows various functions such as accelerated signal processing tasks to be integrated into the instruction set, which can handle up to five different instructions. System designers use Altera's SPOC Builder tool to automatically create the interface logic between Nios system units, assign a free opcode to it, and generate all the required C and assembler macros.
The design environment for the Nios processor includes parameterized hardware descriptions and an adaptive software development environment. Altera devices such as Cyclone, Stratix, Stratix GX, and HardCopy devices can implement Nios processors. Typical Nios processor performance in FPGAs ranges from 50 to 125 MIPS. Operating systems supported by Nios soft-core processors include ATI Nucleus, uC/OSII, and KROS.
Programmable System (SOPC) Design
Designers use Altera's SOPC Builder tool to generate the desired system in a simple step-by-step manner. First, the CPU for processing is selected - in this case, the Nios architecture. The processor is then configured by setting different architectural features. The most important parameters include:
Data bus width
Register set size
Arithmetic functions supported by the hardware (such as multiplication)
Performance or size optimization
Support for operating system-
specific instructions (division, floating point unit, FFT and others)
The CPU has been tailored to the expected system requirements, and the designer only needs to create the interfaces required by the Nios control system. With the help of a graphical user interface, the required system is built from a complete library of different modules. The interface library includes IP cores used by the device and modules provided by Altera IP partners. It is also possible to add dedicated modules to the module list, which can later become a standard block for a specific user group.
Each IP module is parameterized using its own programming mask. In this process, the module is adjusted according to the set data bus width, its function is controlled, or it is optimized for a specific application. For example, the taps and coefficients of the FIR filter can be adjusted to meet the specific needs of a diversity TV receiver.
The next step is to connect the functional modules to the CPU. First, the internal bus system is generated graphically, the interface modules are connected to the CPU, and the address ranges and interrupts are assigned. In this way, the necessary elements required for the entire system are set up and the system is realized.
On the hardware side, Altera SOPC Builder generates a network list, VHDL or Verilog description and simulation environment. On the software side, SOPC Builder automatically creates program header files, libraries and drivers required for the interface to be incorporated into the program environment.
The last step is to integrate the Nios design into the PLD, write the application, synthesize the system and libraries with the operating system, and program the target system. All these steps will be completed in the Quartus II integrated development environment, which can also be used for the final verification and debugging stage.
The next goal of digital TV development
In the future, Hirschmann plans to integrate other digital standards such as ISDB T (Japan) and ATSC (USA) into the system. Hirschmann is also studying the concept of "antenna bottom receiver", that is, the receiver is located at the bottom of the antenna. This arrangement can eliminate the need for RF feed lines and amplifiers, thereby further improving the reception quality. Converting part of the receiver hardware to software can configure different broadcast services through software.
Such software radio is based on a consistent hardware platform, so that the entire series of receiver derivatives can be adjusted, configured and used by software over a wide frequency range. The concept of software radio requires that the broadcast signal is scanned between antennas and that all subsequent processing takes place in the digital domain. Software radio in this sense is not yet possible, because the required system processing performance cannot be achieved and, above all, the high sampling frequencies required for the analog-to-digital converters are simply not available. However, a subset of software radio operating at approximately intermediate frequencies may now be well established. Due to the satisfactory quality and convenience of this radio technology, it is likely that it will soon be equipped in new passenger cars.
The author,
Dr. Axel Zimmermann, studied electrical engineering at the University of Stuttgart. After many years of experience as an application engineer for programmable logic in various manufacturing companies, he is now responsible for coordinating automotive projects in Central Europe for Altera GmbH. He is the Regional Sales Manager for Altera GmbH.
Dr. Ing. Wolfgang Sautter has been working as a development engineer in the automotive communication systems department at Hirschman Electronics GmbH & C. KG in Neckartenzlingen, Germany, since 1998. Among other projects, he was responsible for the development of mobile TV receivers.