Interface Design between ARM CPU S3C44B0X and C54X DSP

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Interface Design between ARM CPU S3C44B0X and C54X DSP [Copy link]

1 Features of ARM CPU S3C44B0X

ARM is a 32-bit reduced instruction set (RISC) processor architecture, which occupies the market with its high performance, low power consumption and low cost. Since ARM operates by IP licensing, almost all major semiconductor companies in the world have ARM-based SOC chips.

S3C44B0X is a SOC chip based on ARM7TDMI produced by SAMSUNG. On the one hand, it has all the advantages of ARM processors: low power consumption and high performance; on the other hand, it has very rich on-chip resources, which is very suitable for the development of embedded products. Its features are as follows:

·Adopt ARM7TDMI core, I/O voltage 3.3V, core voltage 2.5V;

Built-in phase-locked loop (PLL), system frequency up to 66MHz;

· 4 working modes, which can realize power management to reduce system power consumption;

8KB system cache (CACHE), which greatly improves the system operation speed;

Supports 8 memory banks, with a maximum external storage space of 256MB and supports SDRAM;

Built-in color LCD controller;

·2-way asynchronous serial port (UART);

71 general-purpose I/O ports;

8-channel analog-to-digital converter (ADC);

Real-time clock (RTC) and watchdog circuit (WATCHDOG).

2 C54X DSP and its HPI interface

2.1 Features of C54X DSP

The C54X series DSP, characterized by high speed and low power consumption, adopts an advanced improved Harvard structure with separate data bus and program bus, and integrates ROM, RAM and multiple peripherals on the chip, such as general I/O ports, timers, clock generators, software programmable wait state generators, programmable block switching logic, serial ports, direct memory access controllers (DMA) and host interfaces (HPI) for communicating with external processors.

2.2 C54X Host Interface (HPI)

There are three main host interfaces (HPI) in C54X: standard 8-bit HPI8 interface, enhanced 8-bit HPI8 interface and 16-bit HPI16 interface. C542~C549 contain standard HPI8; C5402 and C5410 contain enhanced HPI8; C5410 and above contain HPI16; C5409 and C5416 HPI can be set by the user to enhanced HPI8 or HPI16. The main advantage of enhanced type over standard type is that enhanced type allows the host to access all on-chip RAM inside DSP, while standard type can only access the specified 2K words in the RAM area.

Taking the enhanced HPI8 interface included in the TMS320C5416 (C5416 for short) as an example, it has 8 separate data lines HD0~HD7 and 10 controllers for connection with the external host or microprocessor. The host actively accesses the internal RAM and other resources of the DSP through the HPI port. Except for sending interrupts to the host (by setting the HINT bit of the HPIC register, the HINT line can be made valid) or clearing the interrupt sent by the host (by clearing the DSPINT flag of the HPIC register), which requires DSP intervention, C5416 requires almost no other operations. The DMA channel on the chip will automatically assist in completing the data transfer between the RAM area and the HPI data register. The host selects a control register of the HPI by the HCNTL0/1 line, as listed in Table 1. By accessing these 4 registers, all or part of the DSP's on-chip RAM can be read/written within the scope allowed by the set security mechanism.

Table 1 Description of the selection function of HCNTL0/1

HCNTL1	HCNTL0	illustrate
0	0	The host reads/writes the HPI control register --HPIC.
0	1	The host reads/writes the HPI data latch -- HPID in the mode of automatic address increment. If it is a read operation, the HPI address register HPIA automatically increases by 1 after reading; if it is a write operation, HPIA automatically increases by 1 after writing.
1	0	The host reads/writes the HPI address register -- HPIA, which points to the on-chip RAM of the C54X.
1	1	The host reads/writes the HPI data latch--HPID, HPIA remains unchanged.

Since the smallest storage unit of DSP is word (16bit), for HPI8, each transfer must have 2 transfer cycles to complete. The HBIL signal is used to distinguish whether the transferred byte is the first byte or the second byte of the current word. By setting the BOB bit of the HPIC register, it can be determined whether the first byte is the high byte or the low byte of the word.

2.3 Timing Diagram

The timing of C54X HPI8 is shown in Figure 1. This timing can meet the timing characteristics of most microcontrollers on the market. Therefore, C54X can be easily interfaced with microcontrollers through HPI8, and S3C44B0X is no exception.

3 Interface Design between S3C44B0X and C54X DSP

3.1 Hardware Connection

The interface circuit connecting TMS320C5416 and S3C44B0X is shown in Figure 2. As can be seen from Figure 2, when C54X is connected to the host device through HPI8, except for the 8-bit HPI data bus and control signal line, no other logic circuit is required, which is very convenient.

From the addressing method of the HPI register, it can be seen that the host only needs two address lines (A3, A2) to address all the control registers, address registers and data registers of the HPI interface. At the same time, the HPI8 interface is arranged in BANK2 of S3C44B0X (that is, the address range 0X04000000~0X05FFFFFF), and S3C44B0X has an internal decoder to directly generate the chip select signal nGCS2. Since C54X HPI8 is an 8-bit parallel port and the internal structure of C5416 is 16-bit, the host must read/write two consecutive 8-bit bytes, and the host should also provide HBIL signal to indicate whether the first byte or the second byte is transmitted. In S3C44B0X, address line A1 can be used directly to complete this function: when writing data to the address of A1=0, it is represented as the first byte; writing data to the address of A1=1 represents the second byte.

In addition, there are several key control signal lines that need to be connected. One is the HR/W signal. Since S3C44B0X does not have this signal, address line A4 is used instead. When A4=1, it represents a read operation, and vice versa, it represents a write operation. In the operation of HPI8, all address lines and control lines are sampled at the falling edge of HDS1/2, and the read/write signals nOE and nWE of S3C44B0X are used to complete this function.

Since the control logic of the HPI interface of S3C44B0X and C5416 is different, some other signal lines need to be used for simulation. At this time, the read and write timing of HPI must be strictly followed (as shown in Figure 1).

3.2 Software Design

Since the host interface (HPI) transmits 8-bit data bytes, and the HPIC register (usually the register that S3C44B0X needs to address first) is a 16-bit register, the HPIC register can be managed with the same high byte and low byte of the content on the S3C44B0X side (although the addressing of some bits is subject to certain restrictions), and the high bit is not used on the C54X side.

When the host starts to access DSP data, it must first perform the following two steps:

·The BOB bit of the HPIC register is set to 1 (the high byte and the low byte must be the same). The BOB bit is the byte selection bit. The BOB bit is set to 1, indicating that the first byte is the low byte. The BOB bit affects the transmission of data and addresses. Only the host can modify this bit, and the C54X can neither read nor write it.

·Write the starting address into the HPIA register.

After that, the data in the DSP's internal RAM can be accessed normally.

By combining the hardware design and HPI operation steps, it is possible to write a program on S3C44B0X to implement data communication with C5416.

The program is mainly divided into two parts: one is the definition of address and data; the other is the implementation code. The specific program is as follows:

#define HPI_BASE 0x4000000

/* HPIC reg */

#define HPIC_W_F *(UINT8*)(HPI_BASE+0x0) //000 0 0

#define HPIC_W_S *(UINR8 *)(HPI_BASE +0x2) //000 1 0

#define HPIC_R_F *(UINT8 *) (HPI_BASE + 0x10) //110 0 0

#define HPIC_R_S *(UNIT8 *)(HPI_BASE+0x12) //110 1 0

/*define HPID_W_A_F *(UINT8 *)(HPI_BASE +0x4) //001 0 0

#define HPID_W_A_S * (UINT8 *) (HPI_BASE + 0x6) //001 1 0

#define HPID_R_A_F *(UINT8 *) (HPI_BASE+0x14) //101 0 0

#define HPID_R_A_S *(UINT8 *)(HPI_BASE + 0x16) //101 1 0

/* HPIA reg */

#define HPIA_W_F *(UINT8 *)(HPI_BASE + 0x8) //010 0 0

#define HPIA_W_S *(UINT8 *)(HPI_BASE +0xA) //010 1 0

#define HPIA_R_F *(UINT8 *)(HPI_BASE +0x18) //110 0 0

#define HPIA_R_S *(UINT8 *)(HPI_BASE + 0x1A) //110 1 0

The above macros define the address of the HPI8 interface register. For S3C44B0X, HPI8 occupies BANK2 of its memory, that is, the starting address is 0X04000000. Since the HR/W and HBIL signals of HPI8 are implemented using the address lines of S3C44B0X, the read and write addresses of the same register are different.

The following code reads data from the DSP:

UINT16 read_dsp(UINT16 addr)

{

INT16 i;

INT8 j;

set_hpia(addr); //Set the starting address

i=HPID_R_A_F; //Read the first byte

j=HPID_R_A_S; //Read the second byte

return (i<<8)|(j&0xff);

}

The following code writes data to the DSP:

void write_dsp(UINT16 addr,UINT16 dat)

{

set_hpia(addr-1); //Set the starting address

HPID_W_A_F = (UINT8) ((dat>>8) & 0xff); // Write the first byte

HPID_W_A_S = (UINT8) (dat & 0xff); // write the second byte

}