Design of Continuous Modulation Mode Power Factor Corrector

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Design of Continuous Modulation Mode Power Factor Corrector [Copy link]

The traditional method of obtaining DC voltage from a 220V AC power grid through uncontrolled rectification has been widely used in power electronics technology. Its advantages are simple structure, low cost and high reliability. However, this uncontrolled rectification causes serious distortion of the input current waveform, which is in the form of a pulse near the voltage peak and contains a large number of harmonic components. On the one hand, it causes serious pollution to the power grid and interferes with the normal operation of other electronic equipment; on the other hand, it also greatly reduces the power factor of the entire circuit, which can usually only reach 0.5 to 0.7.

The solution to this problem is to suppress the height of the current pulse and make the current waveform as close to a sine wave as possible. This technology is called power factor correction. Power factor ( PF ) refers to the ratio of active power ( P ) to apparent power ( S ), that is:

PF = ×cosΦ=γcosΦ

Therefore, the power factor can be defined as the product of the current distortion factor (γ) and the phase shift factor (cosΦ).

Power factor correction technology, from the perspective of its implementation method, is to make the grid input current waveform completely track the grid input voltage waveform, so that the input current waveform is a sine wave (γ=1) and is in phase with the voltage waveform (cosΦ=1). In an ideal situation, the rectifier load can be equivalent to a pure resistor, and the PF value is 1.

Power factor correction technology can be roughly divided into passive and active types. Considering the large size and poor performance of passive PFC, this article only discusses the methodological aspects of active power factor correction (APFC) technology.

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1 APFC technology implementation method and characteristics 1.1 Basic structure of APFC circuit 1.1.1 Buck type, such as UC3871, is rarely used because of its high noise, difficulty in filtering, large voltage stress on the power switch tube, and easy floating of the control drive level. 1.1.2 Boost/buck type, such as TDA4815 and TDA4818, requires two power switch tubes, one of which has a floating drive control signal. The circuit is complex, so it is rarely used. 1.1.3 Flyback type, such as ML4813, has output isolation from input, and the output voltage can be selected arbitrarily. It uses simple voltage type control and is suitable for low-power applications below 150W. 1.1.4 Boost type This method is widely used. Its characteristics are simple current type control, high PF value, small THD, and high efficiency, but the output voltage is higher than the input voltage. It is suitable for applications in the power range of 75 to 2000W and is the most widely used. It has the following advantages: the inductor L in the circuit is suitable for current type control; because the pre-adjustment of the boost APFC maintains a high voltage on the output capacitor C, the capacitor C is small in size and has a large energy storage capacity; it can maintain a high power factor within the entire range of AC input voltage variation; the input current is continuous, and the input current is small at the moment of APFC switching, which is easy to filter EMI; the boost inductor L can prevent transient changes in voltage and current, thereby improving the reliability of the circuit. 1.2 Control principle of input current in APFC circuit 1.2.1 Average current type For example, ML4832 and UC3854 have a constant operating frequency and adopt continuous modulation mode (CCM). The operating waveform is shown in Figure 1. The advantages of this control method are constant frequency control; working in the continuous state of inductor current, the effective value of the switch tube current is small, and the EMI filter is small in size; it can suppress switching noise; and the input current waveform has small distortion. The main disadvantages are that the control circuit is complex; multipliers and dividers must be used; the inductor current must be detected; and a current control loop is required. Figure 1 Average current type 1.2.2 Peak current type Such as ML4831, MC34262, the operating frequency is constant, CCM, and the operating waveform is shown in Figure 2. Figure 2 Peak current type 1.2.3 Hysteresis current type Such as CS3810, the operating frequency is variable, CCM, the current reaches the hysteresis band, the power switch is turned on or off, and the input current increases or decreases. The average value of its current waveform depends on the inductor input current, and the operating waveform is shown in Figure 3. Figure 3 Hysteresis current type 1.2.4 Voltage tracking control type Such as ML4813, SG3561, the operating frequency is variable, and the discontinuous modulation mode (DCM) is adopted. Its operating waveform is shown in Figure 4. DCM adopts the follower method, which has the advantages of simple circuit and easy implementation, but it also has the following disadvantages: the power factor is related to the ratio of input voltage Vin to output voltage VO, Vin/VO, that is, when Vin changes, the power factor PF will also change. At the same time, the increase of Vin/VO increases the THD of the input current waveform; the peak current of the switch tube is large (under the same capacity, the peak current passing through the switch tube in DCM is twice that of CCM), which leads to increased loss of the switch tube. Therefore, in high-power applications, APFC based on CCM is more advantageous. Figure 4 Voltage tracking control type

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2 Design Method of CCMAPFC Circuit Based on the analysis of the characteristics of the above various schemes, it can be known that in the application of 75~2000W power, it is more suitable to select the average current type BoostAPFC circuit working in the continuous modulation mode. In the specific circuit design, the control chip is UC3854A (its internal structure is shown in Figure 5), which is a high power factor correction integrated control circuit chip produced by Unitrode. Its peak switching current is approximately equal to the input current, and its response to transient noise is extremely small. It is an ideal APFC control chip. Figure 5 UC3854A internal structure diagram 2.1 Technical indicators Input voltage Vin = AC 150~265V; Output voltage VO = DC 400V; Power supply frequency f = 47~65Hz; Output power PO = 2kW; Switching frequency fs = 50kHz. 2.2 Switching frequency High switching frequency can reduce the structural size of the PFC circuit, improve power density, and reduce distortion; but too high a frequency will increase switching losses and affect efficiency. In most applications, a switching frequency of 20 to 300kHz is a good compromise. In this design, the switching frequency is selected to be 50kHz, so that the inductance is reasonably sized, the peak distortion is small, the physical size of the inductor is small, and the power loss on the MOSFET and Boost Diode is not excessive. In higher power PFC designs, appropriately reducing the switching frequency can reduce switching losses. The operating frequency of the oscillator is determined by equation (1). fs= (1) 2.3 Selection of Boost Inductor The inductor determines the size of the input current ripple, and its inductance is given by the specified ripple current. The maximum peak current occurs at the peak of the minimum line voltage and is given by equation (2). ILINE(PK)=×P／Vinmin（2） The peak-to-peak ripple current in the inductor is usually selected to be around 20% of the maximum peak line current, that is, ΔI=ILINE(PK)×20%（3） The duty cycle at the lowest input voltage peak is D=（4） Therefore, the value of the inductor should satisfy L>（5） 2.4 Selection of output capacitor The following factors should be considered when selecting the output capacitor: ripple current of the switching frequency, second harmonic current, DC output voltage, ripple output voltage and hold time, etc. The hold time Δt refers to the length of time that the output voltage remains within the specified range after the input power is turned off. Its typical value is generally 15 to 50ms. Under this principle, the selected capacitor must ensure that CO>（6） 2.5 Selection of switch tube and boost diode The switch tube and boost diode must have sufficient rating to ensure reliable operation of the circuit. The rated current of the switch tube must be greater than the maximum peak current on the inductor, and a certain margin should be left. The same is true for the boost diode. The trr of the boost diode must be small enough to reduce the loss of the switch when it is turned on, and at the same time reduce the loss of the diode. To reduce the trr of the diode, two 300V fast recovery diodes can be connected in series, and a high resistance resistor can be added to maintain voltage balance. 2.6 Selection of current detection resistor IPK(max)=ILINE(PK)＋（7） RS=（8） Generally, a 1V resistor voltage drop is selected, which can have good noise resistance and will not produce too much loss. 2.7 Setting of multiplier The multiplier is the core of power factor correction. The output of the multiplier is used as the input of the current loop regulator, and a high power factor is obtained by controlling the input current. Therefore, the output of the multiplier is a signal expressing the input current, and its expression is IMO=（9） Where: IMO is the output current of the multiplier; IAC is the input current of the multiplier; VVEA is the output of the voltage error amplifier; Vff is the feedforward voltage; KM is a constant equal to 1. 2.8 Design of current control loop The open loop of current control loop is a first-order integral system, as shown in Figure 6. In order to make the system run stably, the current loop must be compensated. The zero point of the current regulator must be at or below the maximum cut-off frequency fCI, at which point the system has a phase margin of 45°. In order to eliminate the system's sensitivity to noise at the switching frequency, a pole should be introduced into the current regulator. The frequency of the pole is 1/2 of the switching frequency. When the pole frequency is greater than 1/2 of the switching frequency, the pole will not affect the frequency response of the current loop. Therefore, the following characteristics should be met when designing the current loop: 1) The open loop of the current loop is a first-order integral system, and should have as high a low-frequency gain as possible to reduce the steady-state error; 2) The loop should have as high a crossover frequency as possible to achieve fast following; 3) The loop should exhibit attenuation characteristics at the switching frequency to eliminate the switching noise in the loop; 4) The loop should have sufficient stability margin to make the circuit robust. Figure 6 APFC circuit diagram (current loop) 2.9 Design of voltage control loop In order for the circuit to work stably, the voltage control loop must be compensated. However, because the bandwidth of the voltage control loop is smaller than the switching frequency, the requirement for the voltage control loop is mainly to ensure that the input distortion is minimized. First, the bandwidth of the loop must be low enough to attenuate the second harmonic of the grid frequency on the output capacitor and ensure that the modulation amount of the input current is small; second, the voltage error amplifier must have sufficient phase shift so that the modulated signal can keep in phase with the input voltage, thereby obtaining a higher power factor. The voltage loop is a first-order integral system, as shown in Figure 7. In order to reduce the distortion caused by the second harmonic current, the voltage error amplifier must introduce a pole for compensation to reduce the amplitude of the harmonic voltage and provide a 90° phase shift. The minimum cutoff frequency of the voltage loop is fVI= (10) Figure 7 APFC circuit diagram (voltage loop) Its typical bandwidth is 10~30Hz, and the phase margin is 45~70°. In actual design, in order to ensure good stability of the output voltage, the cut-off frequency should be selected slightly higher, and the voltage loop should have a phase margin slightly greater than 45°.

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3 Experimental Data and Waveforms The performance of the APFC circuit designed with the above parameters was tested. The input voltage range was 150-265V and the maximum output power was close to 2200W. Figures 8, 9 and Table 1 show the experimental data and some test waveforms. Fig.8 PFC input voltage and current waveformFig.9 Output voltage waveform at startupTable 1 Experimental dataAC Input (AC input) DC Output (DC output) THD (Total Harmonic Distortion) Vrms/V Ifund/A Pin/W PF Vo/V Io/A Po/W η/％ THD/％ 150 3.47 518 0.992 396.9 1.25 497 95.86 10.03 220 2.36 516 0.993 396.7 1.25 497 96.37 8.89 265 1.95 514 0.993 396.5 1.26 498 96.88 8.92 150 5.98 895 0.995 396.5 2.15 853 95.36 6.39 220 4.07 891 0.993 396.3 2.16 856 96.11 8.66 265 3.34 888 0.992 395.9 2.17 858 96.67 9.98 150 7.12 1066 0.9 92 395.8 2.57 1017 95.44 9.93 220 4.81 1059 0.991 395.6 2.58 1021 96.45 10.88 265 3.99 1053 0.993 395.3 2.59 1024 97.23 8.99 150 10.41 1556 0.992 395.1 3.76 1484 95.36 10.01 220 7.05 1541 0.994 394.8 3.78 1492 96.79 7.78 265 5.87 1535 0.994 3 94.7 3.79 1494 97.36 7.97 150 14.73 2197 0.992 394.5 5.32 2099 95.53 9.84 220 10.04 2184 0.993 394.3 5.37 2118 96.97 8.87 265 8.35 2175 0.995 394.2 5.39 2126 97.74 6.58 Experiments show that the APFC circuit designed with this scheme works stably and can meet the design requirements well: the instantaneous value of the input current follows the instantaneous value of the input voltage, the current waveform is approximately a sine wave and is in phase with the voltage waveform, the power factor (PF) of the circuit is above 0.99, and the total harmonic distortion (THD) is <10%; when the load changes, the voltage value at the DC output terminal remains basically constant; when the voltage at the AC input terminal changes, the load power remains basically constant.

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Based on the Boost circuit topology, this paper adopts the average current control method of continuous modulation mode (CCM) and selects UC3854A as the control core to design an active power factor correction circuit. Experiments have shown that this scheme can not only obtain a stable DC output but also achieve power factor correction by reasonably configuring the circuit parameters in applications with medium and higher power. This design principle is also applicable to the circuit implementation of other APFC control chips of the same type, and has the advantages of simple circuit structure, small size, stable and reliable operation, etc. It has broad application prospects in occasions where power factor control is required under medium and higher power.