A High-Speed CMOS Fully Differential Operational Amplifier

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A High-Speed CMOS Fully Differential Operational Amplifier [Copy link]

A High-Speed CMOS Fully Differential Operational Amplifier

Zhu Xiaozhen, Zhu Zhangming, Chai Changchun

(Institute of Microelectronics, Xidian University, Xi'an 710071, China)

1 Introduction The operational amplifier (op amp) is one of the most common units in analog circuits. The so-called fully differential op amp refers to an op amp whose input and output are both differential signals. Compared with ordinary single-ended output op amps, it has the following advantages: lower noise; larger output voltage swing; better suppression of common-mode noise; better suppression of even-order terms of harmonic distortion, etc. Therefore, high-performance op amps are mostly in fully differential form. In recent years, the higher unity gain bandwidth frequency and larger output swing of fully differential op amps have made it more attractive for applications in high-speed and low-voltage circuits. With the increasing data conversion rate, many applications require high-speed analog-to-digital converters (ADCs), and high-speed ADCs require high-gain and high unity gain bandwidth op amps to meet their system accuracy and fast settling requirements. Speed and accuracy are the two most important performance indicators of analog circuits. However, optimizing these two aspects of the circuit will lead to contradictory results [1] . Therefore, it is difficult to meet both requirements at the same time. Folded cascode technology can successfully solve this problem. The op amp of this structure has a higher open-loop gain and a very high unity gain bandwidth. The disadvantage of a fully differential op amp is that the common-mode loop gain of its external feedback loop is very small and the output common-mode level cannot be accurately determined. Therefore, an additional common-mode feedback loop is often necessary. The circuit containing a common-mode feedback loop is called a common-mode feedback circuit (CMFB) [2,3] . 2. Selection of circuit structure To design a fully differential operational amplifier, we must first select a suitable circuit structure according to its purpose. For high-speed operational amplifiers, we hope that it has the highest possible unity gain frequency under low power supply voltage, and we must also consider the performance limitations of open-loop gain, settling time, input common-mode range, output swing, common-mode rejection ratio, power supply rejection ratio, power consumption, etc. Figure 1 shows several common fully differential operational amplifiers [4-6] . Figure 1 (a) shows a simple two-stage fully differential operational amplifier, whose differential output swing is 2V sup -4V ds,sat , where V sup is the power supply voltage and V ds,sat is the minimum V ds of the transistor working in the saturation region . Obviously, its output swing is the largest among various fully differential operational amplifier structures. The disadvantages of this structure are poor frequency characteristics (small bandwidth, limited speed), high power consumption, and poor power supply rejection ratio and common mode rejection ratio. Figure 1(b) is a sleeve-type common-source common-gate fully differential op amp, which has the following advantages: good frequency characteristics, because its secondary pole value is gm3 / C L1 , C L1 is the parasitic capacitance of the source node of M3 or M4, and its value is much smaller than C L in Figure 1(a) , so the secondary main pole of Figure 1(b) is much larger than the secondary main pole of Figure 1(a), resulting in wider bandwidth and faster speed; the power consumption is the lowest among all structures, because this structure has only two current branches. Disadvantages: The common-mode input range and output swing are too small, which is not suitable for low-voltage operation. Figure 1 (c) is a folded common-source common-gate fully differential op amp. Its advantages are mainly: the frequency characteristics are similar to the sleeve-cascade structure, because its secondary pole value is g m9 /C L1 , C L1 is the parasitic capacitance of the drain node of M 10 or M 11 , which is similar to Figure 1 (b); the common-mode input range and output swing are much larger than the corresponding values of the sleeve-cascade structure. The output swing is 2V sup－8V ds,sat－4V margin , and the common-mode input range is V T +V ds,sat <V incom <V sup . Disadvantages: There are 4 current branches, and the power consumption is greater than the sleeve-cascade structure. From the application point of view, the designed op amp requires the highest possible speed. The above analysis shows that both the folded cascode op amp and the telescopic cascode op amp structures have higher speeds, but the folded cascode op amp has a larger output swing than the telescopic cascode op amp structure. This advantage is obtained at the cost of greater power consumption, lower voltage gain, lower pole frequency, and higher noise. Nevertheless, the folded cascode op amp is more widely used than the telescopic cascode op amp structure. Because its output and input can be short-circuited, and the input common-mode level is easier to select, the folded cascode op amp structure is more in line with our design requirements. 3 Folded Cascode Operational Amplifier The folded cascode op amp structure is shown in Figure 2(a). M1 and M2 are input driver transistors (the use of p-tube input is mainly because the op amp can have a better frequency characteristic, because the non-main pole of the folded cascode op amp is at the drain of the input tube, the parasitic capacitance of the p-tube input is smaller than that of the n-tube input, and the frequency characteristic is better. In addition, since the noise generated by the p-tube is smaller than the noise generated by the NMOS tube, the noise performance of this structure is also better than that of the n-tube input structure), M6 and M7 form a folded cascode transistor. Common-mode feedback is obtained by controlling the bias voltage of M4 and M5. The common-mode feedback circuit includes M12 to M19, and two differential pairs (M14, M15 and M16, M17) convert their differential current into a current mirror load M18, M19, and output from M18. In order to maximize the output signal swing, the common-mode reference voltage value is usually half of the voltage source [6,7] . In order to make the amplifier stably biased under the desired conditions, the bias circuit needs to be optimized. Figure 2(b) shows the bias circuit that meets the requirements of the operational amplifier. 3.1 Large Signal Analysis of Op Amp By selecting the appropriate bias voltage, the low end of the output swing is V OD5 +V OD7 and the high end is V DD -(|V OD9 |+|V OD10 |). Therefore, the swing between the two peaks of the op amp side is equal to V DD -(V OD5 +V OD7 +|V OD9 |+|V OD10 |). M4 and M5 flow large currents, and if their contribution to the capacitance of the source terminals of M6 and M7 is to be minimized, a higher overdrive voltage is required. 3.2 Small Signal Analysis of Op Amp The small signal voltage gain of the op amp is: |A v |=G m R out , where the output resistance R out ≈[(g m9 +g mb9 )r o9 r o10 ]||[(g m7 +g mb7 )r o7 (r o1 ||r o5 )] G m ≈g m1｛[(g m9 +g mb9 )r o9 r o10 ]||[(g m7 +g mb7 )r o3 (r o1 ||r o5 )]｝ Assuming that C L1 , C L2 , and C L3 are the total capacitances at the drain nodes of M7, M10, and M5 respectively, the frequency of the main pole is where C L3 depends mainly on C gs7 . Since there is a zero approximately equal to -g m9 /C L2 , the effect of P 3 is canceled. Unity gain frequency: g m1 = ω 0 C L 摆率：ISS=2SR?CL(ISS=IS3) Phase margin: g m7 =ω 0 C L1 tan(PM) Power consumption: P DISS =(2I casc +I SS )V DD These theoretical relationships provide a direct means to estimate the parameters of CMOS op amps. The ultimate goal of the design is to directly obtain the width-to-length ratio of the op amp based on performance requirements. The W/L ratio can be obtained through the following relationship: 4 Simulation Results Based on the folded cascode fully differential operational amplifier circuit shown in Figure 2, the folded cascode operational amplifier is simulated using the Spectre simulator using the TSMC 0.25μm CMOS process. When the power supply voltage is 2.5V, the operational amplifier is subjected to AC analysis, large signal step response transient analysis, and transfer characteristic analysis, and the characteristic curves are shown in Figures 3 to 5. The frequency characteristic curve shows that when driving a load of 0.5pF, the operational amplifier can achieve a gain of 71.9dB and a unit gain bandwidth of 495MHz. Table 2 shows the simulation results of some important performance parameters. 5 Conclusion This paper designs a high-speed fully differential CMOS operational amplifier using folded cascode technology and continuous-time common-mode feedback structure. The simulation results show that a DC open-loop gain of 71.9dB, a unity-gain bandwidth of 495MHz, and a settling time of 24ns can be obtained under a single power supply voltage of 2.5V, which meets the application requirements of high-speed operational amplifiers and can be applied to fields such as high-speed A/D converters.