Cadence Launches Space-Based, Full-Chip and Module Routing Solutions

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Cadence Launches Space-Based, Full-Chip and Module Routing Solutions [Copy link]

Cadence Design Systems, Inc. recently announced the launch of space-based, full-chip and module routing solutions. Cadence Precision Router is aimed at advanced mixed-signal, analog and custom digital designs. In order to achieve design performance closure and achieve mass production faster, it allows designers to model manufacturing-related effects during the design process.

Complex interconnect rules, including those in 65- and 45-nm designs, pose a great challenge to the physical modeling capabilities of traditional shape-based and grid routers . Cadence Precision Router uses a 3D-based modeling approach to analyze real shapes and physical space interference to address the design complexity caused by increasing design size and shrinking process geometries. Compared to shape-based methods, the models used by Cadence Precision Router have higher accuracy, precision and flexibility in creating, verifying and processing interconnects, and simplify the integration of design and manufacturing.

According to reports, Cadence Precision Router can be seamlessly integrated with the Virtuoso custom design platform to provide a closed environment for hierarchical, constraint-driven design with high incremental interactive and automatic routing capabilities. The architecture can combine electrical performance indicators to optimize hierarchical and preferred manufacturing rules, helping designers achieve high-quality design results in a short period of time. The silicon-proven results of Cadence Precision Router show exponential improvements in performance and capacity. In addition, for large-scale designs that are prevalent in cutting-edge process nodes, Cadence Precision Router also has multi-threaded routing capabilities to speed up the design cycle.

"Cadence Precision Router has reduced time to closure compared to our previous design approach," said Mark Papermaster, vice president of Microprocessor and Systems Technology Development at IBM. "Using the hierarchical constraint system in the solution, we have been able to handle complex manufacturing and high-performance design constraints and achieve high-quality results. As an early partner in Cadence's next-generation space-based interconnect system, we see the value of having a single platform for interconnect optimization and creation for both design for manufacturability and high-yield design. As a result, we have already adopted Cadence Chip Optimizer and Cadence Precision Router in our 65-nanometer and 45-nanometer microprocessor designs."

As process geometries continue to shrink, designers must adapt to evolving design rules, meet electrical performance indicators, manage growing design sizes, and even perform extremely time-consuming manual adjustments after routing. To meet these challenges, Cadence Precision Router provides a gridless, three-dimensional space-based routing architecture. This solution overcomes the limitations of shape-based routers in performance and capacity, as well as the limitations of grid-based routers in accuracy and flexibility, allowing designers to model advanced manufacturing processes and design constraints for the front end of the design process to obtain optimal control and excellent results. Cadence Precision Router also features professional mixed-signal routing, incremental in-core electrical analysis, as well as design for manufacturability and high-yield design optimization, making it particularly suitable for high-performance module-level and full-chip designs.

Cadence Precision Router and Cadence Chip Optimizer are based on innovative technologies developed in Cadence's "Catena" technology incubator program and can be widely applied to a variety of design types and process nodes. By using Cadence Precision Router in the design flow, integrated device manufacturers (IDMs) have achieved 45nm node tapeouts in the consumer, commercial and computing markets.

“Process variability, increasingly complex design rules, and manufacturing effects from lithography and chemical mechanical polishing have become paramount considerations in design,” said Ted Vucurevich, chief technology officer of Cadence Advanced Research and Development. “To address these issues, we developed a new architectural approach for Cadence Precision Router that allows designers to see the physical, electrical and logical views simultaneously. This approach is the cornerstone of convergence, paving the way for designers to achieve the quality of results, high capacity and high pass yields required for routing of future advanced designs.”

Cadence Precision Router is part of Cadence's growing family of design and manufacturing closure technologies , helping designers address design performance as well as manufacturing and yield issues throughout the design process. Cadence Precision Router is based on the industry-standard OpenAccess open database and can seamlessly connect to the Virtuoso custom design platform and complement the Encounter digital IC design platform.