Libero IDE 7.2 increases flexibility for Actel FPGA-based designs

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Libero IDE 7.2 increases flexibility for Actel FPGA-based designs [Copy link]

Actel公司宣布推出Actel Libero集成设计环境(IDE)的最新版本7.2，具备崭新功能，可提升基於Actel现场可编程门阵列(FPGA)设计的灵活性、效率和性能。LiberoIDE7.2具有强化的SmartGen、SmartTime和SmartPower工具，提供全新的知识产权(IP)核生成功能，以支持Actel的Fusion可编程系统芯片(PSC)产品。Libero IDE7.2还同时为ActelFusion、ProASIC3和RTAX-S系列产品的设计人员，提供增强的时序和功率分析功能。

Actel应用解决方案高级市务总监莊正一说：“随着越来越多的系统工程师转向FPGA，LiberoIDE7.2能让这些设计人员全面发挥Fusion平台的功能，而不论是否使用系统级芯片(SoC)、混合信号、分立或模拟设计环境。Actel的承诺是要为客户提供能提升设计人员效率和FPGA器件性能的工具，新推出的IDE具备崭新的SmartGen、SmartTime和SmartPower功能，可以满足设计人员的设计需求之余，并同时降低成本和提高整个系统的可靠性。”

Intelligent tools assist FPGA design

For many commonly used IP functions, the SmartGen tool brings design automation features to users, allowing designers to import existing IP cores and create new IP cores for Fusion-based designs. New features include a sample sequencer, sample sequencer configuration circuits, and a graphical phase-locked loop (PLL) configurator. In addition, the state management function that monitors module changes and interrelated information can now pass the obtained information directly to Libero, allowing designers to update all related modules with a single click of the mouse. SmartGen now supports direct updates to non-volatile memory used to configure analog system components, thereby reducing or eliminating lengthy synthesis iterations.

Actel's SmartTime timing analysis tool provides static timing analysis based on industry standards, including Synopsys's design constraints SDC, and a new graphical constraint interface, making the transition from ASIC to mixed-signal FPGA easier. Another new feature is clock source hysteresis analysis, which allows the definition of constraints on clocks with jitter, helping designers analyze the timing of FPGAs in their operating environment. SmartTime can also perform correctness checks on the recovery and removal of asynchronous signals for internal and externally generated clocks.

Enhancements to Actel's SmartPower power analysis tool allow users to perform detailed power analysis, thereby helping to save power, reduce costs and improve the reliability of designs. SmartPower can now generate power consumption information for nets, system gates, I/O, RAM, FIFOs and clock circuits separately, or generate power consumption information for each module based on component type. The tool can perform power distribution checks and power comparisons for all defined voltages. In addition, SmartPower can estimate the timing and output power of each load based on the startup rate, allowing designers to calculate system power consumption more accurately.

ActelLiberoIDE7.2Platinum (Platinum) version can run on Windows and Unix platforms; the upgraded LiberoGold (Gold) version is used on Windows platform. All versions provide a one-year renewable license. For more information on product prices, please contact Actel.