Microcontrollers that improve power efficiency in 8051 systems

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Microcontrollers that improve power efficiency in 8051 systems [Copy link]

Abstract: A high-performance 8051 design with improved architecture, peripheral function integration, and selection of appropriate clock sources to reduce power consumption; and introduces software technology for saving power and techniques for reducing power consumption using standby mode.

Keywords: shutdown mode, idle mode, power management mode

The functions and performance of portable products are changing with each passing day. Consumers are also increasingly demanding product performance, requiring more powerful computing power support; on the other hand, they hope that the product has lower power consumption.

Although many power-saving processors have emerged, their performance is usually limited. Dallas' series of high-speed microcontrollers have achieved a good compromise between performance and power consumption, using the 8051 architecture, one of the most popular microcontrollers in the world. The ease of use and rich I/O resources make this microcontroller popular among designers and widely accepted. Its popularity has spread to the portable field and has found its place in many applications.

This article aims to explore how to reduce power consumption when using the 8051 controller, focusing on a high-performance 8051 design with an improved architecture.

1 Clock frequency

In any microcontroller design, one of the primary factors that determines power consumption is the system's clock frequency. The power consumption of devices in complementary metal oxide semiconductor (CMOS) processes is directly proportional to the clock frequency. Therefore, from a power saving perspective, it is beneficial to run the processor at the lowest possible frequency.

Figure 1 shows a typical power curve for a common 8051 microcontroller, a relationship that is well known to all portable system designers. Generally speaking, the current vs. frequency curve is linear with a certain DC offset. This quiescent current is consumed by the static circuits on the chip, such as comparators, operational amplifiers, etc. Its value is generally small (<1mA), and it is a non-negligible fixed absorption current.

Any power-constrained design should consider using the slowest possible operating speed. There are many factors that determine the minimum system frequency, and therefore the lowest power consumption, including the desired system performance, interrupt response latency, etc. Regardless of the criteria used, the ultimate goal is the same: to make the device's operating frequency as close as possible to the application's requirements.

2 High-speed core

The most direct way to reduce the power consumption of 8051-based systems is to improve the efficiency of microcontrollers. The original design of 8051 used a 12-clock cycle, two instruction fetches per machine cycle architecture. However, high-speed microcontrollers use cores with 4 or even 1 clock per machine cycle. They have higher computing efficiency, require fewer clock cycles to execute an instruction, and have faster operating speeds and higher clock frequencies.

Although the advantages of high-speed cores are usually considered in terms of processing power, they have an important significance in reducing power consumption. When the processor's execution instructions are optimized, the time required to perform the same task is very short. Many portable products work in burst mode, which is characterized by only a short period of activity, such as recording environmental data or scanning a bar code, and then being inactive for a long time. Reducing the active time of the processor can reduce power consumption accordingly.

Another benefit of increased efficiency is that a lower clock frequency can be required to achieve the same performance. If a redesigned core uses a 4-clock machine cycle instead of 12 clocks, this means that a lower crystal frequency is required to complete the same work. Since power is proportional to crystal frequency, power consumption can be reduced without sacrificing performance.

图2显示三种微控制器以同样的速度完成同一任务时的功耗情况。其中两种是标准80C3X的衍生产品：一种是工作于每机器周期12个外部时钟方式；另外一种是DS80C320微控制器，工作于4时钟机器周期。测出各个器件的消耗电流，然后进行对比，保守地估计DS80C320具有250%（2.5倍）的速度提升。正如图2所显示的，每周期时钟数减少后的处理器内核工作于同样的吞吐率时，消耗的电流显著降低，高速运行时尤其显著。

3. Integration

Integrating peripheral functions into the chip is one way to save power. When driving a signal outside the chip, the processor core with a reduced number of clocks per cycle works at the same throughput rate in order to drive external loads and compensate for DC losses. Switching power is a function of the power consumed during the transition of digital signals. Switching power can be estimated according to the following formula:

PSW∝CV2/T （1）

Where C is the sum of the input capacitance of the receiving gate and the wiring capacitance, and T is the clock signal period. A typical input capacitance of a CMOS gate is 10pF. Although it is difficult to accurately calculate the switching power of a system, it is clear that every additional external load or pin will cause additional power consumption in the microcontroller.

Microcontroller-based systems usually have a certain number of peripheral devices, from external UARTs and power-on bit circuits to watchdog timers. One of the advantages of the 8051 series is that a large number of peripheral functions are integrated on-chip. In addition to reducing the number of components and simplifying the design, the integration of peripheral functions also helps to reduce power consumption. It can be assumed that the core function of any peripheral device consumes the same power, regardless of whether it is located inside or outside the processor. However, placing the function on-chip undoubtedly saves the switching power required to drive the external bus.

3.1 Internal Program Memory

Another 8051 feature that is not usually considered a peripheral is the program memory. All 8051 derivatives include varying amounts of on-chip program memory. This is desirable in many system designs to reduce the number of peripheral components and printed circuit board area, while also improving power life in portable systems. As mentioned earlier, integrated program memory reduces power consumption by eliminating the need for external bus drivers. There is another reason to save power by using on-chip memory. The 8051 architecture requires the use of a 74373 type latch to latch the low byte address. Figure 3 shows the power consumption when using internal and external program memory. The former uses a DS87C520 high-speed microcontroller and a 74AC573 latch, as well as a 27C256 EPROM with a 70ns access time. The second system uses the same microcontroller, operating from internal memory. Both systems run at 11.0592MHz and execute a simple, common program. As can be seen from Figure 3, the elimination of the external EPROM and latch in the high-frequency system can save up to 49mA of current.

3.2 Internal Data Memory

As mentioned earlier, using on-chip memory instead of external RAM can save power. 80C32 derivatives have expanded temporary memory (256 bytes), which is small enough for program stack operations and data storage without external RAM.

For designs that require more data storage or to set up an external stack, additional SRAM is required. Although low-power SRAM can be found, the power consumption it brings should also be considered along with the associated 74373 series latches, capacitive losses driving the external bus, etc.

4 Clock Source

影响功耗的另一个重要的系统元素是时钟源。标准8051设计通常采用内部振荡器激励一个外部石英晶体产生时钟，或者采用外部晶体振荡器。如果采用外部晶体振荡器，时钟的波形会影响到功耗。如果采用外部晶体振荡器，时钟的波形会影响到功耗。XTAL1引肚子内的输入级用来将外部时钟信号输入8051内核，通常采用互补式驱动器。随着输入时钟在高、低电平之间的跳动，驱动器中的互补对管会有一个短时间的同时开通过程，造成显著的电流浪涌。对于矩 形波来说，高、低状态之间的过渡过程非常短暂，两管同时开通的时间最短。对于上升和下降时间比较长的波形，例如正弦或三角波，过渡过程比较长，驱动器两管同时开通的时间也更长。这将会增加电流和功耗。

Figure 4 shows the relationship between current consumption and waveform. The clock source is a programmable waveform generator that can generate sine, triangle, or square waves. The current shown in Figure 4 is the average of four devices, including traditional and improved high-speed processing cores. The comparison shows that the current consumption is directly proportional to the rise (and fall) time of the clock waveform. The triangle wave has the smallest slope, while the rectangular wave has the largest slope. The current when using the rectangular wave is 0.75mA lower than the triangle wave on average. This indicates that when using an external clock oscillator, using an oscillator with faster rise and fall times will help reduce current consumption. This is especially important at lower frequencies, when the device needs to spend more time in the transition process.

Some 8051 derivatives include an on-chip ring oscillator. This is usually a series of inverters through which the pulses propagate. This can provide a 2-4MHz internal clock source to drive the device. Since no crystal is required, this oscillator is a very low power clock source. The characteristics of the DS87C520 high-speed microcontroller can be seen, when operating from a ring oscillator, it can provide the same performance as a 7MHz 8051, while consuming only 3.6mA. Although ring oscillators are not as stable as piezoelectric crystals, their low pull-down and negligible power-up delay play a prominent role in power management.

5 Clock Management

The operating frequency of the microcontroller is the most important factor affecting the power consumption of the device. Although the system clock frequency depends mainly on the hardware configuration, the 8051 still provides some limited control methods. These methods slow down or stop the operating clock of all or part of the device. The traditional 8051 architecture uses two control methods: idle and shutdown.

5.1 Improved shutdown mode

Stop mode is the lowest power state that the 8051 is designed to use. In this mode, the internal oscillator is stopped and the device stops working. Exiting stop mode is usually done by external reset. Some variants can also exit stop mode by external interrupt.

One disadvantage of shutdown mode is the power consumption during the dead time when the crystal oscillator resumes operation. The operation of the crystal oscillator depends on the vibration of the quartz crystal. The physical layer limitations determine that the crystal oscillator must have a certain time to reach sufficient oscillator amplitude to drive the device to work. This warm-up process exists regardless of whether the internal oscillator or the external oscillator is used. The time is about 3 to 12ms, which is related to the performance of the crystal and oscillator.

预热过程对于功耗的作用在于，在此阶段器件不执行任何有用的工作，但仍要消耗功率。如果器件频繁地进入和退出停机模式，或者退出停机模式后只执行很短时间的任务，这种效应会变得格外显著。事实上，如果任务非常短（<5ms），晶振启动期间消耗的能量甚至会超过执行任务本身的消耗。如果采用环形振荡器来实现从停机模式到快速启动，就可避免这种延迟。这将大幅降低退出停机模式时的功率消耗。
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图5表示两个系统退出停机模式并执行一个短任务时的工作情况。其中一个器件包含一个内置的环形振荡器，另一个使用传统的外部晶振。没有环形振荡器的器件必须经历一个晶振预热期。在此期间器件不断地消耗功率，却没有做任何有用的工作。第二个器件是一片DS87C520高速微控制器，片内包含一个环形振荡器。这就允许器件在退出停机模式时能立即恢复工作。在本例中，程序执行4ms以内，间隔大约为2MHz。正如图5所看到的，当需要退出停机模式执行短任务时，采用环形振荡器可以大幅减少能量消耗。

In some applications, the clock needs to be as stable as a crystal oscillator soon after exiting shutdown mode. In this case, a ring oscillator still has its advantages. Immediately after exiting shutdown mode, the controller should start the crystal oscillator immediately. The controller can then initialize some necessary data or registers during the crystal warm-up period. Most high-speed microcontrollers can use a status bit to indicate whether the crystal oscillator has reached stability. Once the initialization process of the crystal oscillator code is completed, the software can query the status bit to decide whether to proceed with high-precision timing operations.

Another way to improve the efficiency of stop mode is to use an interrupt rather than a reset to wake up the controller. This allows the processor to resume work immediately following the instruction that sets the STOP bit, rather than restarting from the reset vector. This eliminates the need to determine the cause of the reset, allowing the processor to start useful work in the shortest possible time.

5.2 Idle Mode

Idle mode is the second clock management mode used in the early 8051 architecture. This mode stops the CPU from running, but the general timer on the chip keeps working. In power-sensitive applications, this timer is used to periodically wake up the processor to perform tasks, or to determine whether a task should be performed.

Since the standard 8051 timer is 16 bits, the maximum timing period is only 31ms when the clock frequency is 16MHz. If a longer period is required, the timer needs to overflow multiple times. This consumes additional power because the processor must frequently resume full speed operation to accumulate counts but does not perform any useful work.

For longer periods, it is better to use an internal timer with a longer timing period. Some 8051 derivatives include a watchdog timer that can also be used to wake up the processor. The watchdog timer can be programmed for a longer timing, up to 256 clock cycles. It can provide a maximum delay of 4.2s at a frequency of 16MHz. Suppose an application wants to wake up from a low-power state every 3s to perform a task. If an internal timer is used for timing, the processor will have to exit idle mode 96 flashes without doing useful work. If a watchdog timer with a long timing period is used, the processor only needs to exit the idle state when performing a task and return to the low-power state after completing the task.

Another option is to use a microprocessor with a real-time clock (RTC). The built-in RC of the DS87C530 high-speed microprocessor can generate an alarm signal with a period of up to 24 hours. The internal interrupt generated by the alarm can wake up the processor from idle or stop mode. Using RTC to exit stop mode is the most effective way for systems that need to be suspended for a long time.

6 Power Management Modes

Although idle mode reduces power consumption by suspending the running program, the internal timer is still running continuously at the frequency of the external clock. This consumes a considerable amount of power. Imagine if you could run the timer in a state that is basically close to standby.

A better approach is to reduce the clock frequency of the entire device. This can be achieved by an internal clock divider, which divides the external clock frequency before sending it to the CPU. This solution has been implemented in the DS87C520 high-speed microcontroller. The device uses two clock division factors: power management mode 1, the input clock source is divided by 64; power management mode 2, the input clock source is divided by 1024. These modes can be achieved by setting the corresponding bits in the special function register.

Figure 6 compares the clock dividers and clock control modes of the DS87C520 high-speed microcontroller. In Figure 6, the current consumption in full-speed mode (divide by 4), power management mode 1 (divide by 64), power management mode 2 (divide by 1024), idle mode, and stop mode are compared. As expected, the stop mode draws the lowest current because all internal clocks are turned off. Both power management modes consume less current than the idle mode. This not only reduces the power consumption of the device, but also means that it can be operated continuously at a lower level. In the traditional 8051 architecture, there are only two states for any type of CPU operation: "all or nothing". The processor is forced to frequently run at the highest performance level, although the high performance is only achieved for a short period of time, which can increase unnecessary power consumption. The use of power management modes (PMMs) allows the processor (such as the system) to optimize its power consumption based on the actual performance requirements.

6.1 Interrupts and PMM Usage

The problem with using an internal clock divider is that interrupt latency is greatly increased; in addition, the slowing down of the internal timer affects the ability of the 8051 serial port to generate or synchronize to a standard baud rate. This can seriously interfere with the processor's ability to respond to external stimuli. One solution is to automatically restore the processor to a fully operational state after an external interrupt or serial port activity is acknowledged. This solution has been implemented in the DS87C520. This processor's switchback feature allows it to respond quickly to external interrupts. Immediately following the interrupt reply, the device will automatically switch back to full speed (divide by 4) without software intervention.

The serial ports operate in a very similar manner. When a falling edge (start bit) is detected on the serial port receive pin, the device automatically switches back to full speed operation (divided by 4). This process immediately follows the start of the data transfer, so the device can correctly receive the rest of the transfer at full speed. With the traditional 8051 architecture, the only way to use the serial port in a low power configuration is to utilize the idle mode. The use of power management modes provides a lower power alternative.

6.2 Improved burst working mode

In low-power designs, the most common operating mode is to wake the processor from stop mode, perform a burst task, and then return to stop mode. In such a system, one means of reducing power consumption is to increase the operating frequency. At first glance, this seems incredible. Because during normal operation, a high-frequency system consumes more power than a low-frequency system. However, the quiescent current consumed by the system when it is operating is independent of the frequency. In a final design, its energy consumption is usually evaluated to determine the battery operating life. This is particularly critical when evaluating a high-performance microcontroller because it takes into account both processing time and processing power. For a given system, if it has a smaller power-time product, then it consumes less energy; it is not necessary to consider the two parameters separately. Many examples show that high-speed microcontrollers actually consume less energy due to shorter operating time; while low-speed processors with longer processing time are just the opposite.

This can be verified by referring to Figure 6. Assume that after recovering from the shutdown mode, the DS87C520 reads an I/O port, performs arithmetic operations and sends the result out of another port. This process requires 500 machine cycles of CPU time. As shown in Figure 6, the current consumption is 12.4mA at 10MHz and 34.6mA at 30MHz. Table 1 summarizes the energy consumption when performing read tasks at the two speeds. As can be seen from Table 1, the efficiency is higher when working at 30MHz, and the energy consumption is reduced by more than 6%.

Table 1 Comparison of energy consumed when executing a 500 machine cycle task and processor speed

Clock frequency	Machine Cycle	Machine cycles used	Total time	Icc	Current-time product
10MHz	400ns	500	200ms	12.41mA	2.48 mAs
30MHz	133ns	300	6.5ms	34.66mA	2.30mAs

6.3 Run and Stop

In many applications, the time out of stop mode is not entirely dependent on the operating speed. In many cases, the processor needs to access a peripheral device with a fixed response time, such as an A/D converter or a thermostat. In this case, the processor will have a burst of action. Generally, a process is triggered, followed by a period of time, with little or no operation. At this time, a combination of power saving techniques will be more effective.

An example can be used to illustrate the benefits of using a high-speed microprocessor with PWM in such a system. Consider a DS87C520 interfaced to a DS1620 digital thermometer/thermostat. This device is accessed serially using the standard 8051 serial port in mode 0. At some point, the host processor wakes up the DS87C520 from shutdown mode via an external interrupt and asks it to read the temperature data from the DS1620. Once the data is obtained, the DS87C520 stores it in internal memory for later transmission. The operation of the DS1620 is similar to that of many A/D converters: a command is issued to initiate a conversion, then, after a certain delay, the conversion is complete and the data can be removed. For the DS1620, the conversion time is close to 1 second. The device is polled to determine if the conversion is complete. The DS87C520 is well suited for this task because it can perform the startup and calculation functions very quickly. The microcontroller can then place it in PMM while waiting for the conversion to complete. In the traditional 8051, after the conversion is started, the idle mode can be used to put the traditional 8051 into a low power state. In this mode, the internal 16-bit timer can be used to measure the conversion time. When operating at 16MHz, the traditional 8051 needs to exit the idle mode up to 32 times before the conversion is completed.

本例可被进一步改进。因为DS1620是作为一个同步器件进行访问的，不要求高精度的定时操作。这样，微控制器在启动转换和读取转换结果时，可工作于环形振荡器。由于避免了稳定外部晶振所需的“死时间”，这会进一步节省功率。
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图7展示了两个8051系统执行上述“跑跑停停”任务时的工作情况。正如图7中所看到的，在紧随着退出停机模式的程序运行中，功率节省非常显著。除了因采用PMM2代替空闲模式所带来的功率节省外，晶体预热时间的省略意味着程序可以更快地返回停机模式。在1秒钟的转换延迟期间，采用环振荡器工作很大程度上减慢了处理器的速度，可节省很多功率。

The 8051 series of microcontrollers has always been one of the most popular processors in the world. Its ease of use and relatively high performance are ideal for many applications, including portable and handheld products. The emergence of Dallas high-speed microcontrollers provides a new way to improve the power efficiency of existing 8051 systems without redesigning them.