Actel Releases Libero IDE 7.2

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Actel Releases Libero IDE 7.2 [Copy link]

Actel Corporation has announced the latest version 7.2 of the Actel Libero? Integrated Design Environment (IDE), with new features that improve the flexibility, efficiency and performance of Actel field programmable gate array (FPGA)-based designs. Libero IDE 7.2 features enhanced SmartGen, SmartTime and SmartPower tools, providing new intellectual property (IP) core generation capabilities to support Actel's Fusion? Programmable System-on-Chip (PSC) products. Libero IDE 7.2 also provides enhanced timing and power analysis capabilities for designers of Actel Fusion, ProASIC3 and RTAX-S product families.

"As more and more system engineers turn to FPGAs, Libero IDE 7.2 enables these designers to fully exploit the power of the Fusion platform, regardless of whether they are using a system-on-chip (SoC), mixed-signal, discrete or analog design environment," said Actel's senior director of marketing for application solutions, Zhengyi Zhuang. "Actel is committed to providing customers with tools that improve designer productivity and FPGA device performance, and the new IDE features SmartGen, SmartTime and SmartPower to meet designers' design needs while reducing costs and improving overall system reliability."

For many commonly used IP functions, the SmartGen tool will bring design automation features to users, allowing designers to import existing IP cores and create new IP cores for Fusion-based designs. New features include a sample sequencer, sample sequencer configuration circuitry and a graphical phase-locked loop (PLL) configurator. In addition, the state management function that monitors module changes and interrelated information can now pass the obtained information directly to Libero, allowing designers to update all related modules with a single click of the mouse. SmartGen now supports direct updates of nonvolatile memory used to configure analog system components, thereby reducing or eliminating lengthy synthesis iterations.

Actel's SmartTime timing analysis tool provides static timing analysis based on industry standards, including Synopsys's design constraints SDC, and a new graphical constraint interface, making the transition from ASIC to mixed-signal FPGAs easier. Another new feature is clock source hysteresis analysis, which allows constraints to be defined on clocks with jitter, helping designers analyze the timing of the FPGA in its operating environment. SmartTime can also check the correctness of the timing of asynchronous signal recovery and removal for internally and externally generated clocks.

Enhancements to Actel's SmartPower power analysis tool allow users to perform detailed power analysis, thereby helping to save power, reduce costs and improve the reliability of designs. SmartPower can now generate power information for nets, system gates, I/O, RAM, FIFOs and clock circuits separately, or on a block-by-block basis based on component type. The tool can perform power distribution checks and power comparisons for all defined voltages. In addition, SmartPower estimates the timing and output power of each load based on the startup rate, allowing designers to more accurately calculate system power consumption.

Actel Libero IDE 7.2 Platinum version can run on Windows and Unix platforms; the upgraded Libero Gold version is used for Windows platform. All versions provide a one-year renewable license.