Research on the Setting and Application of 80C51 Reset Flag

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Research on the Setting and Application of 80C51 Reset Flag [Copy link]

Introduction
　　Setting the reset flag bit is convenient for distinguishing resets caused by different reasons. As a new technology, it is adopted by more and more new microcontrollers. For example, Philips' P87LPC700 and P89LPC900 series, Freescale's (formerly Motorola Semiconductor Division) MC68HC05 series and MC68HC08 series, Sunplus's SPMC65 series, Microchip's PIC series, etc., all have internally designed status registers specifically for recording various reset flags.
　　The MC68HC08 series has a reset status register that is responsible for recording 6 reset flags:
power-on reset, pin reset, watchdog reset, illegal instruction reset, illegal address reset, and undervoltage reset. The SPMC65 series has a system control register that is responsible for recording 5 reset flags:
power-on reset, external reset, watchdog reset, illegal address reset, and undervoltage reset. The 51-compatible P89LPC900 series has a reset source register that is responsible for recording 6 reset flags:
undervoltage reset, power-on reset, external reset, watchdog reset, software reset, and UART received interval character reset (mainly as one of the ways to enter the ISP monitoring program). Even the AT89S51/52 and P89C52X2, which are commonly used by beginners, have added a power-on flag POF in their power control register PCON.
1. Setting the reset flag bit
　　The traditional 80C51 microcontroller does not have a reset flag bit recording function, which should be said to be a pity. Can this shortcoming be made up by certain technical means? Here is a revelation and guidance for the majority of 80C51 microcontroller users.
　　The realization of the reset flag bit recording must require certain hardware circuit support, and there is no fixed pattern for the design of this circuit. The author uses a MAX813L to design a support circuit, as shown in Figure 1, for readers' reference only.

Figure 1 80C51 reset flag support circuit
　　In Figure 1, a 4-input "NAND" gate G1 and a push button switch SW1 are used, and the 5 I/O pins P1.0~P1.4 of the 80C51 and an external interrupt source INT0 are also occupied.
In advance, INT0 is set as the only high-level interrupt source through the initialization software, the falling edge trigger mode is valid, and the general interrupt enable bit EA is opened. Usually, G1 maintains a high level because all input terminals are maintained at a high level, so its output terminal also maintains a high level. A massive capacitor C1 is used in the circuit as an energy storage device, playing the role of a backup battery. Due to the presence of diode D1, during the power failure of the main power supply, C1 only supplies power to the microcontroller, and the 80C51 should be allowed to enter the shutdown state (PD mode) with the lowest energy consumption.
　　Based on the circuit in Figure 1 and with the necessary user software, 6 flag bits can be saved to record 7 reset flags after 7 different reset sources cause a reset. The following will explain them separately. A byte can be allocated in advance in the bit addressing range of the RAM, such as unit 20H, to record the six reset flag bits, as listed in Table 1.
Table 1 User-defined system reset flag register (SRFR)

　　Assume that the register is named SRFR (System Reset Flag
Register), the byte address is 20H, and only 6 bits are used out of 8 bits. Bit5~bit0 record manual reset, undervoltage reset, watchdog reset, illegal address reset, hardware and software reset, and software reset respectively.
　　① MRST:
Manual reset. When the reset button SW1 is pressed, the INT0 interrupt is triggered; the state of the input pin P1.4 is detected in the interrupt service program. If P1.4=0, MRST is set to
record that a manual reset operation has occurred. Then an active reset operation is performed by outputting a low level from the output pin P1.0 to the input pin MR of the MAX813L, and after a delay by the MAX813L, a high level reset signal is sent from the output terminal RESET to the 80C51, causing it to perform a hardware reset operation.
　　② LVR:
Undervoltage reset. When the upstream power supply voltage begins to drop and drops below the PFI detection threshold of the MAX813L, the output terminal PFO sends a low level, triggering the INT0 interrupt; the state of the input pin P1.3 is detected in the interrupt service program. If P1.3=0, then set LVR to record that an undervoltage reset operation has occurred; then perform an active reset operation (same method as above), or put the microcontroller into shutdown state to save energy and maintain data, and wait for the main power supply to be restored.
　　③ WDR:
Watchdog reset. When a watchdog overflow occurs, the output terminal WDO of MAX813L sends a low level, triggering the INT0 interrupt; in the interrupt service program, detect the state of the input pin P1.2. If P1.2=0, set WDR to record that a watchdog reset operation has occurred; then perform an active reset operation (same method as above). The dog feeding operation uses an I/O pin P1.1.
　　④ IAR:
Illegal address reset. When an illegal address occurs, the output terminal PSEN of 80C51 sends a low level instantaneous pulse, which will also trigger an INT0 interrupt; in the interrupt service program, detect the state of the input pins P1.4~P1.2. If P1.4~P1.2=111, IAR is set, indicating that an illegal address reset operation has occurred; then an active reset operation is performed (the method is the same as above).
　　⑤ SHR:
Software and hardware reset. When a software trap capture event occurs, or a software watchdog overflow event occurs, SHR can be directly set to indicate that a software and hardware reset operation has occurred; then an active reset operation is performed (the method is the same as above). If T0 is used as a software WDT, the INT0 and T0 interrupt sources should be set to high-level interrupts at the same time.
　　⑥ SWR:
Software reset. When a software trap capture event occurs, or a software watchdog overflow event occurs, SWR can also be directly set to indicate that a software reset operation has occurred; then the software reset program SWRST can be called. The writing method of the software reset program is as follows:
SWRST:; Define the actual entry address of the software reset program
　　CLREA; First turn off the interrupt source enable bit
　　SETBF0; Set a software reset flag
　　MOVP0, #0FFH; Set the general port P0 to high-impedance input state
　　MOVP1, #0FFH; Set the general port P1 to high-impedance
　　input state MOVP2, #0FFH; Set the general port P2 to high-impedance input state
　　MOVP3, #0FFH; Set the general port P3 to high-impedance input state
　　MOVPSW, #00H; Set the program status word register to the original value
　　; (Other SFRs can also be initialized as needed)
　　MOVDPTR, #SWR0; Prepare the pop-up address for RETI without changing
　　the execution order
　　PUSHDPL; Push the low byte on the stack, first
　　PUSHDPH; Push the high byte on the stack, then
　　RETI; Interrupt return instruction, clear the high-level interrupt activation trigger
　　SWR0
:
　　CLRA; Prepare the reset address
　　PUSHACC; Push the low byte 00H
　　PUSHACC; Push the high byte 00H
　　RETI; clear the low-level interrupt activation trigger and jump to
　　; 0000H
　　⑦ POR:
Power-on reset. Although a POR flag is not directly set in the user-defined system reset flag register (SRFR), if the above 6 flags are detected to be 0 at the same time, it indicates that a power-on reset was performed before. The reason is that after experimental verification (the microcontroller model used in the experiment is SST89C58), at the first power-on, the contents of the 80C51 internal RAM area (00H~7FH), including the 20H unit of RAM, are all automatically cleared to zero; each time the RST pin is reset (or software reset), its content remains unchanged. Regardless of whether it is a power-on reset or a RST pin reset, each SFR is restored to its original value (also called reset value), as listed in Table 2.
Table 2 Reset of on-chip rewritable memory space

　　For those newer microcontrollers (such as AT89S51/52, AT89S8252, AT89C53, AT89C55WD, AT89C51RC and P89C51X2/52X2/54X2/58X2, etc.) that only add a reset flag (recorded as POF in the technical manual), the POR flag set here is no longer needed.
　　For microcontroller application systems that are not equipped with a backup power supply, you can also consider using E2PROM to transfer the reset flag at the moment before power failure so that it will not disappear completely after power failure. In this case, you can choose a circuit solution with an external E2PROM data storage (such as 8-pin serial 24C01, 93C46 or 25C040, etc.), or you can choose a microcontroller model with an internal E2PROM data storage, such as AT89S8252, etc. In this way, the burning operation of E2PROM can be completed by using a small amount of residual energy on the power filter capacitor C2 at the moment before power failure.
2 Application method of reset flag bit
　　The general method of writing initialization program paragraph is very simple, but it is only suitable for those single-chip microcomputer projects with low requirements and simple functions. Such projects (such as single-chip microcomputer applications such as some small household appliances) almost do not have strong "process" or "continuity", and the reset operation that may occur at any time and the user program that is re-run from the beginning will not bring much impact or destructive consequences.
　　For single-chip microcomputer projects with strong "process" or "continuity" requirements, once an accidental reset operation occurs and the user program is re-run from the beginning, it will bring great negative impact or destructive consequences. For example, a bread machine controlled by a single-chip microcomputer will go through stirring, heating and other processes during the process of making bread; if an accidental reset occurs and the program is re-executed from the beginning, it will become waste or burnt. If a computer-controlled surgical robot is accidentally reset and reworked during an operation, it will bring unimaginable serious consequences. If a computer-controlled missile is accidentally reset and the program is re-executed from the beginning during the flight after it is aimed at the target and launched, it will produce unpredictable results.
　　In summary, if it is inevitable that the microcontroller will be reset due to unexpected interference during operation, then where to start running the program or under what background after the reset can be arranged manually. Therefore, the application method of the reset flag is essentially the writing method of the reset handler. The processing flow of the reset handler is shown in Figure 2.

Figure 2 The reset processing procedure
　　is similar to the idea of writing a UART serial communication interrupt service program. After entering the interrupt program, the interrupt flag bit must be checked first to see if it is a receive interrupt (RI=1) or a send interrupt (SI=1), and then different program branches must be entered for targeted services. As can be seen from Figure 2, when executing the user program from the reset vector 0000H, the reset flag register should be checked first to determine whether it is the initial power-on of the power supply or the reset or program counter PC clearing caused by other reset sources.
　　① If it is the initial power-on of the power supply, the original state is initialized. This situation is the simplest.
　　②
If it is a software reset, software and hardware reset, illegal address reset, or manual forced reset caused by program runaway, the data should be restored or the parameters should be corrected as much as possible according to the specific situation, so as to minimize or minimize the impact on the normal operation of the program (the specific algorithm for restoring and correcting data will not be discussed in depth here).
　　③ If it is an undervoltage reset, try to restart the program from the interrupted program breakpoint. The specific implementation method and steps can be:
before reset - after the MCU responds to the PFO interrupt request and enters its service program, the current value of the stack pointer SP is saved to the specified RAM unit, and the MCU is pushed into the shutdown state; after reset - after the power is restored, MAX813L is powered and sends a high-level signal from the RESET terminal to wake up the MCU in the shutdown state. If the awakened MCU detects that it is an undervoltage reset, it will first restore the previous SP value, and then use a RET (or RETI) instruction to pop up the program breakpoint before the shutdown to the PC, so that the previous task can continue to be executed.